Nec PD78F9488 User Manual

User’s Manual µPD789488 µPD789489 µPD78F9488 µPD78F9489 µPD789489 Subseries 8-Bit Single-Chip Microcontrollers Printed in Japan

10 User’s Manual U15331EJ4V1UD Documents Related to Flash Memory Writing Document Name Document No. PG-FP3 Flash Memory Programmer User’s Manual U

CHAPTER 5 CLOCK GENERATOR 100 User’s Manual U15331EJ4V1UD (4) Subclock selection register (SSCK) (µPD78F9488, 78F9489 only) This register is us

CHAPTER 5 CLOCK GENERATOR User’s Manual U15331EJ4V1UD 101 5.4 System Clock Oscillators 5.4.1 Main system clock oscillator The main system cl

CHAPTER 5 CLOCK GENERATOR 102 User’s Manual U15331EJ4V1UD 5.4.2 Subsystem clock oscillator The subsystem clock oscillator is oscillated by the

CHAPTER 5 CLOCK GENERATOR User’s Manual U15331EJ4V1UD 103 5.4.3 Example of incorrect resonator connection Figure 5-9 shows examples of incorre

CHAPTER 5 CLOCK GENERATOR 104 User’s Manual U15331EJ4V1UD Figure 5-9. Examples of Incorrect Resonator Connection (2/2) (e) Signal is fetched

CHAPTER 5 CLOCK GENERATOR User’s Manual U15331EJ4V1UD 105 5.5 Clock Generator Operation The clock generator generates the following clocks and

CHAPTER 5 CLOCK GENERATOR 106 User’s Manual U15331EJ4V1UD 5.6 Changing Setting of System Clock and CPU Clock 5.6.1 Time required for switching

CHAPTER 5 CLOCK GENERATOR User’s Manual U15331EJ4V1UD 107 5.6.2 Switching between system clock and CPU clock The following figure illustrates

108 User’s Manual U15331EJ4V1UD CHAPTER 6 16-BIT TIMER 20 6.1 16-Bit Timer 20 Functions 16-bit timer 20 has the following functions. • Time

CHAPTER 6 16-BIT TIMER 20 User’s Manual U15331EJ4V1UD 109 Figure 6-1. Block Diagram of 16-Bit Timer 20 CPT20/TO20/INTP3/P33Internal busInte

User’s Manual U15331EJ4V1UD 11 CONTENTS CHAPTER 1 GENERAL ...

CHAPTER 6 16-BIT TIMER 20 110 User’s Manual U15331EJ4V1UD (4) 16-bit counter read buffer 20 This buffer is used to latch and hold the count v

CHAPTER 6 16-BIT TIMER 20 User’s Manual U15331EJ4V1UD 111 Figure 6-2. Format of 16-Bit Timer Mode Control Register 20 Symbol <7> <

CHAPTER 6 16-BIT TIMER 20 112 User’s Manual U15331EJ4V1UD (2) Port mode register 3 (PM3) This register is used to set the I/O mode of port 3

CHAPTER 6 16-BIT TIMER 20 User’s Manual U15331EJ4V1UD 113 6.4 16-Bit Timer 20 Operation 6.4.1 Operation as timer interrupt 16-bit timer 20

CHAPTER 6 16-BIT TIMER 20 114 User’s Manual U15331EJ4V1UD Figure 6-5. Timing of Timer Interrupt Operation CR20INTTM20TO20TOF20NN N NNt0000HNF

CHAPTER 6 16-BIT TIMER 20 User’s Manual U15331EJ4V1UD 115 6.4.2 Operation as timer output 16-bit timer 20 can invert the timer output repeat

CHAPTER 6 16-BIT TIMER 20 116 User’s Manual U15331EJ4V1UD 6.4.3 Capture operation The capture operation consists of latching the count value

CHAPTER 6 16-BIT TIMER 20 User’s Manual U15331EJ4V1UD 117 6.4.4 16-bit timer counter 20 readout The count value of 16-bit timer counter 20 (

CHAPTER 6 16-BIT TIMER 20 118 User’s Manual U15331EJ4V1UD 6.5 Cautions on Using 16-Bit Timer 20 6.5.1 Restrictions when rewriting 16-bit com

CHAPTER 6 16-BIT TIMER 20 User’s Manual U15331EJ4V1UD 119 <Countermeasure B> When rewriting using 16-bit access <1> Disable inte

12 User’s Manual U15331EJ4V1UD 3.1.4 Data memory addressing ...

120 User’s Manual U15331EJ4V1UD CHAPTER 7 8-BIT TIMERS 50, 60, AND 61 7.1 Functions of 8-Bit Timers 50, 60, and 61 One 8-bit timer channe

CHAPTER 7 8-BIT TIMERS 50, 60, AND 61 User’s Manual U15331EJ4V1UD 121 (5) PPG output mode (PPG: Programmable Pulse Generator) Pulses are

CHAPTER 7 8-BIT TIMERS 50, 60, AND 61 User’s Manual U15331EJ4V1UD 122 7.2 Configuration of 8-Bit Timers 50, 60, and 61 8-bit timers 50, 6

CHAPTER 7 8-BIT TIMERS 50, 60, AND 61 User’s Manual U15331EJ4V1UD 123Figure 7-2. Block Diagram of Timer 50 TEG50TCL500TCL5018-bit timer m

CHAPTER 7 8-BIT TIMERS 50, 60, AND 61 User’s Manual U15331EJ4V1UD 124 TCE60TCL602 TCL601 TCL600TMD601TMD600 TOE6008-bit timer mode control

CHAPTER 7 8-BIT TIMERS 50, 60, AND 61 User’s Manual U15331EJ4V1UD 125TCE61TCL612 TCL611 TCL610TMD611TMD610 TOE6108-bit timer mode controlr

CHAPTER 7 8-BIT TIMERS 50, 60, AND 61 User’s Manual U15331EJ4V1UD 126 Figure 7-5. Block Diagram of Output Controller (Timer 60) F/FRMC60

CHAPTER 7 8-BIT TIMERS 50, 60, AND 61 User’s Manual U15331EJ4V1UD 127(4) 8-bit H width compare registers 60 and 61 (CRH60, CRH61) In carr

CHAPTER 7 8-BIT TIMERS 50, 60, AND 61 User’s Manual U15331EJ4V1UD 128 7.3 Control Registers for 8-Bit Timers 50, 60, and 61 8-bit timers

CHAPTER 7 8-BIT TIMERS 50, 60, AND 61 User’s Manual U15331EJ4V1UD 129Figure 7-6. Format of 8-Bit Timer Mode Control Register 50 (2/2) Sym

User’s Manual U15331EJ4V1UD 13 5.4.5 When subsystem clock is not used ...

CHAPTER 7 8-BIT TIMERS 50, 60, AND 61 User’s Manual U15331EJ4V1UD 130 Figure 7-7. Format of 8-Bit Timer Mode Control Register 60 Symbol &

CHAPTER 7 8-BIT TIMERS 50, 60, AND 61 User’s Manual U15331EJ4V1UD 131(3) Carrier generator output control register 60 (TCA60) This regist

CHAPTER 7 8-BIT TIMERS 50, 60, AND 61 User’s Manual U15331EJ4V1UD 132 (4) 8-bit timer mode control register 61 (TMC61) 8-bit timer mode c

CHAPTER 7 8-BIT TIMERS 50, 60, AND 61 User’s Manual U15331EJ4V1UD 133(5) Port mode register 3 (PM3) This register is used to set the I/O

CHAPTER 7 8-BIT TIMERS 50, 60, AND 61 User’s Manual U15331EJ4V1UD 134 7.4 Operation of 8-Bit Timers 50, 60, and 61 7.4.1 Operation as 8-

CHAPTER 7 8-BIT TIMERS 50, 60, AND 61 User’s Manual U15331EJ4V1UD 135Table 7-3. Interval Time of Timer 50 TCL502 TCL501 TCL500 Minimum I

CHAPTER 7 8-BIT TIMERS 50, 60, AND 61 User’s Manual U15331EJ4V1UD 136 Figure 7-11. Timing of Interval Timer Operation with 8-Bit Resoluti

CHAPTER 7 8-BIT TIMERS 50, 60, AND 61 User’s Manual U15331EJ4V1UD 137Figure 7-13. Timing of Interval Timer Operation with 8-Bit Resolutio

CHAPTER 7 8-BIT TIMERS 50, 60, AND 61 User’s Manual U15331EJ4V1UD 138 Figure 7-15. Timing of Interval Timer Operation with 8-Bit Resoluti

CHAPTER 7 8-BIT TIMERS 50, 60, AND 61 User’s Manual U15331EJ4V1UD 139Figure 7-16. Timing of Interval Timer Operation with 8-Bit Resolutio

14 User’s Manual U15331EJ4V1UD 9.4.1 Operation as watchdog timer ...

CHAPTER 7 8-BIT TIMERS 50, 60, AND 61 User’s Manual U15331EJ4V1UD 140 (2) Operation as external event counter with 8-bit resolution (time

CHAPTER 7 8-BIT TIMERS 50, 60, AND 61 User’s Manual U15331EJ4V1UD 141(3) Operation as square-wave output with 8-bit resolution Square wav

CHAPTER 7 8-BIT TIMERS 50, 60, AND 61 User’s Manual U15331EJ4V1UD 142 Table 7-7. Square-Wave Output Range of Timer 60 TCL602 TCL601 TCL

CHAPTER 7 8-BIT TIMERS 50, 60, AND 61 User’s Manual U15331EJ4V1UD 1437.4.2 Operation as 16-bit timer counter Timer 50 and timer 60 can be

CHAPTER 7 8-BIT TIMERS 50, 60, AND 61 User’s Manual U15331EJ4V1UD 144 Table 7-9. Interval Time with 16-Bit Resolution TCL602 TCL601 TCL60

CHAPTER 7 8-BIT TIMERS 50, 60, AND 61 User’s Manual U15331EJ4V1UD 145Interval timeCount clockTM60 count valueCR60TCE60INTTM60TO60FFH 00H7F

CHAPTER 7 8-BIT TIMERS 50, 60, AND 61 User’s Manual U15331EJ4V1UD 146 (2) Operation as external event counter with 16-bit resolution The

CHAPTER 7 8-BIT TIMERS 50, 60, AND 61 User’s Manual U15331EJ4V1UD 147TMI60 pin inputTM60 count valueCR60TCE60INTTM60FFH 00H7FH00HN00HNN N

CHAPTER 7 8-BIT TIMERS 50, 60, AND 61 User’s Manual U15331EJ4V1UD 148 (3) Operation as square-wave output with 16-bit resolution Square w

CHAPTER 7 8-BIT TIMERS 50, 60, AND 61 User’s Manual U15331EJ4V1UD 149 Count clockTM60 count valueCR60TCE60INTTM60TO60NoteFFH 00H7FH00HN00H

User’s Manual U15331EJ4V1UD 15 14.1 Multiplier Function...

CHAPTER 7 8-BIT TIMERS 50, 60, AND 61 User’s Manual U15331EJ4V1UD 150 7.4.3 Operation as carrier generator An arbitrary carrier clock gen

CHAPTER 7 8-BIT TIMERS 50, 60, AND 61 User’s Manual U15331EJ4V1UD 151Figure 7-22. Timing of Carrier Generator Operation (When CR60 = N, C

CHAPTER 7 8-BIT TIMERS 50, 60, AND 61 User’s Manual U15331EJ4V1UD 152 Figure 7-23. Timing of Carrier Generator Operation (When CR60 = N,

CHAPTER 7 8-BIT TIMERS 50, 60, AND 61 User’s Manual U15331EJ4V1UD 153Figure 7-24. Timing of Carrier Generator Operation (When CR60 = CRH6

CHAPTER 7 8-BIT TIMERS 50, 60, AND 61 User’s Manual U15331EJ4V1UD 154 7.4.4 PWM output mode operation (timer 50) In the PWM output mode,

CHAPTER 7 8-BIT TIMERS 50, 60, AND 61 User’s Manual U15331EJ4V1UD 155Figure 7-26. Operation Timing When Overwriting CR50 (When Rising Edg

CHAPTER 7 8-BIT TIMERS 50, 60, AND 61 User’s Manual U15331EJ4V1UD 156 Figure 7-27. Operation Timing in PWM Output Mode (When Both Edges A

CHAPTER 7 8-BIT TIMERS 50, 60, AND 61 User’s Manual U15331EJ4V1UD 157Figure 7-28. Operation Timing in PWM Output Mode (When Both Edges Ar

CHAPTER 7 8-BIT TIMERS 50, 60, AND 61 User’s Manual U15331EJ4V1UD 158 7.4.5 PPG output mode operation (timer 60 and timer 61) In the PPG

CHAPTER 7 8-BIT TIMERS 50, 60, AND 61 User’s Manual U15331EJ4V1UD 159Figure 7-29. PPG Output Mode Timing (Basic Operation) Count clockTM6

16 User’s Manual U15331EJ4V1UD CHAPTER 20 MASK OPTIONS ...

CHAPTER 7 8-BIT TIMERS 50, 60, AND 61 User’s Manual U15331EJ4V1UD 160 7.5 Cautions on Using 8-Bit Timers 50, 60, and 61 (1) Error on sta

User’s Manual U15331EJ4V1UD 161 CHAPTER 8 WATCH TIMER 8.1 Watch Timer Functions The watch timer has the following functions. • Watch timer •

CHAPTER 8 WATCH TIMER 162 User’s Manual U15331EJ4V1UD (1) Watch timer An interrupt request (INTWT) occurs at an interval of 0.5 second when usi

CHAPTER 8 WATCH TIMER User’s Manual U15331EJ4V1UD 163 8.3 Control Registers for Watch Timer The watch timer is controlled by the following r

CHAPTER 8 WATCH TIMER 164 User’s Manual U15331EJ4V1UD (2) Watch timer interrupt time selection register (WTIM) This register is used to set th

CHAPTER 8 WATCH TIMER User’s Manual U15331EJ4V1UD 165 8.4 Watch Timer Operation 8.4.1 Operation as watch timer The main system clock (4.19

CHAPTER 8 WATCH TIMER 166 User’s Manual U15331EJ4V1UD Figure 8-4. Watch Timer/Interval Timer Operation Timing 0HStartOverflow Overflow5-bit co

User’s Manual U15331EJ4V1UD 167 CHAPTER 9 WATCHDOG TIMER 9.1 Watchdog Timer Functions The watchdog timer has the following functions. • Watc

CHAPTER 9 WATCHDOG TIMER 168 User’s Manual U15331EJ4V1UD 9.2 Watchdog Timer Configuration The watchdog timer includes the following hardware.

CHAPTER 9 WATCHDOG TIMER User’s Manual U15331EJ4V1UD 169 9.3 Watchdog Timer Control Registers The watchdog timer is controlled by the follo

User’s Manual U15331EJ4V1UD 17 LIST OF FIGURES (1/6) Figure No. Title Page 2-1 I/O Circuit Types ...

CHAPTER 9 WATCHDOG TIMER 170 User’s Manual U15331EJ4V1UD (2) Watchdog timer mode register (WDTM) This register sets the operation mode of the

CHAPTER 9 WATCHDOG TIMER User’s Manual U15331EJ4V1UD 171 9.4 Watchdog Timer Operation 9.4.1 Operation as watchdog timer The watchdog timer

CHAPTER 9 WATCHDOG TIMER 172 User’s Manual U15331EJ4V1UD 9.4.2 Operation as interval timer When bits 4 and 3 (WDTM4, WDTM3) of the watchdog ti

User’s Manual U15331EJ4V1UD 173CHAPTER 10 10-BIT A/D CONVERTER 10.1 10-Bit A/D Converter Functions The 10-bit A/D converter is a 10-bit res

CHAPTER 10 10-BIT A/D CONVERTER 174 User’s Manual U15331EJ4V1UD Figure 10-1. Block Diagram of 10-Bit A/D Converter ANI3/P63Sample & hold

CHAPTER 10 10-BIT A/D CONVERTER User’s Manual U15331EJ4V1UD 175(3) Sample & hold circuit The sample & hold circuit samples consecu

CHAPTER 10 10-BIT A/D CONVERTER 176 User’s Manual U15331EJ4V1UD 10.3 10-Bit A/D Converter Control Registers The 10-bit A/D converter is cont

CHAPTER 10 10-BIT A/D CONVERTER User’s Manual U15331EJ4V1UD 177Cautions 1. Start conversion (ADCS0 = 1) after 14 µs have elapsed followin

CHAPTER 10 10-BIT A/D CONVERTER 178 User’s Manual U15331EJ4V1UD 10.4 10-Bit A/D Converter Operation 10.4.1 Basic operation of 10-bit A/D con

CHAPTER 10 10-BIT A/D CONVERTER User’s Manual U15331EJ4V1UD 179Figure 10-4. Basic Operation of 10-Bit A/D Converter Conversion timeSamplin

18 User’s Manual U15331EJ4V1UD LIST OF FIGURES (2/6) Figure No. Title Page 5-5 Format of Subclock Control Register...

CHAPTER 10 10-BIT A/D CONVERTER 180 User’s Manual U15331EJ4V1UD Figure 10-5. Relationship Between Analog Input Voltage and A/D Conversion Res

CHAPTER 10 10-BIT A/D CONVERTER User’s Manual U15331EJ4V1UD 18110.4.3 Operation mode of 10-bit A/D converter The A/D converter is initiall

CHAPTER 10 10-BIT A/D CONVERTER 182 User’s Manual U15331EJ4V1UD 10.5 Cautions Related to 10-Bit A/D Converter (1) Current consumption in sta

CHAPTER 10 10-BIT A/D CONVERTER User’s Manual U15331EJ4V1UD 183(5) Timing of undefined A/D conversion result The A/D conversion value may

CHAPTER 10 10-BIT A/D CONVERTER 184 User’s Manual U15331EJ4V1UD (6) Noise prevention To maintain a resolution of 10 bits, watch for noise at t

CHAPTER 10 10-BIT A/D CONVERTER User’s Manual U15331EJ4V1UD 185(9) Interrupt request flag (ADIF0) Changing the contents of A/D converter m

186 User’s Manual U15331EJ4V1UD CHAPTER 11 SERIAL INTERFACE 20 11.1 Serial Interface 20 Functions Serial interface 20 has the following three

CHAPTER 11 SERIAL INTERFACE 20 User’s Manual U15331EJ4V1UD 187 Internal busReceive buffer register 20 (RXB20)Switch of the first bitAsynchro

CHAPTER 11 SERIAL INTERFACE 20 188 User’s Manual U15331EJ4V1UD Clock for receive detectionTransmit shift clockReceive shift clockReceive dete

CHAPTER 11 SERIAL INTERFACE 20 User’s Manual U15331EJ4V1UD 189 (1) Transmit shift register 20 (TXS20) TXS20 is a register in which transmit

User’s Manual U15331EJ4V1UD 19 LIST OF FIGURES (3/6) Figure No. Title Page 7-21 Timing of Square-Wave Output with 16-Bit Resolution ...

CHAPTER 11 SERIAL INTERFACE 20 190 User’s Manual U15331EJ4V1UD 11.3 Serial Interface 20 Control Registers Serial interface 20 is controlled b

CHAPTER 11 SERIAL INTERFACE 20 User’s Manual U15331EJ4V1UD 191 (2) Asynchronous serial interface mode register 20 (ASIM20) ASIM20 is used t

CHAPTER 11 SERIAL INTERFACE 20 192 User’s Manual U15331EJ4V1UD Table 11-2. Serial Interface 20 Operation Mode Settings (1) Operation stop mo

CHAPTER 11 SERIAL INTERFACE 20 User’s Manual U15331EJ4V1UD 193 (3) Asynchronous serial interface status register 20 (ASIS20) ASIS20 indicat

CHAPTER 11 SERIAL INTERFACE 20 194 User’s Manual U15331EJ4V1UD (4) Baud rate generator control register 20 (BRGC20) BRGC20 is used to specify

CHAPTER 11 SERIAL INTERFACE 20 User’s Manual U15331EJ4V1UD 195 The baud rate transmit/receive clock to be generated is either a divided syst

CHAPTER 11 SERIAL INTERFACE 20 196 User’s Manual U15331EJ4V1UD (b) Generation of UART baud rate transmit/receive clock from external clock in

CHAPTER 11 SERIAL INTERFACE 20 User’s Manual U15331EJ4V1UD 197 11.4 Serial Interface 20 Operation Serial interface 20 provides the followin

CHAPTER 11 SERIAL INTERFACE 20 198 User’s Manual U15331EJ4V1UD (b) Asynchronous serial interface mode register 20 (ASIM20) ASIM20 is set with

CHAPTER 11 SERIAL INTERFACE 20 User’s Manual U15331EJ4V1UD 199 11.4.2 Asynchronous serial interface (UART) mode In this mode, the one-byte

2 User’s Manual U15331EJ4V1UD [MEMO]

20 User’s Manual U15331EJ4V1UD LIST OF FIGURES (4/6) Figure No. Title Page 11-4 Format of Asynchronous Serial Interface Mode Register 20 ...

CHAPTER 11 SERIAL INTERFACE 20 200 User’s Manual U15331EJ4V1UD (b) Asynchronous serial interface mode register 20 (ASIM20) ASIM20 is set with

CHAPTER 11 SERIAL INTERFACE 20 User’s Manual U15331EJ4V1UD 201 (c) Asynchronous serial interface status register 20 (ASIS20) ASIS20 is set

CHAPTER 11 SERIAL INTERFACE 20 202 User’s Manual U15331EJ4V1UD (d) Baud rate generator control register 20 (BRGC20) BRGC20 is set with an 8-b

CHAPTER 11 SERIAL INTERFACE 20 User’s Manual U15331EJ4V1UD 203 Table 11-5. Example of Relationship Between System Clock and Baud Rate Error

CHAPTER 11 SERIAL INTERFACE 20 204 User’s Manual U15331EJ4V1UD (2) Communication operation (a) Data format The transmit/receive data format i

CHAPTER 11 SERIAL INTERFACE 20 User’s Manual U15331EJ4V1UD 205 (b) Parity types and operation The parity bit is used to detect a bit error

CHAPTER 11 SERIAL INTERFACE 20 206 User’s Manual U15331EJ4V1UD (c) Transmission A transmit operation is started by writing transmit data to tr

CHAPTER 11 SERIAL INTERFACE 20 User’s Manual U15331EJ4V1UD 207 (d) Reception When bit 6 (RXE20) of asynchronous serial interface mode regist

CHAPTER 11 SERIAL INTERFACE 20 208 User’s Manual U15331EJ4V1UD (e) Receive errors The following three errors may occur during a receive operat

CHAPTER 11 SERIAL INTERFACE 20 User’s Manual U15331EJ4V1UD 209 (f) Reading receive data When the reception completion interrupt (INTSR20)

User’s Manual U15331EJ4V1UD 21 LIST OF FIGURES (5/6) Figure No. Title Page 13-12 Four-Time-Slice LCD Display Pattern and Electrode Connection

CHAPTER 11 SERIAL INTERFACE 20 210 User’s Manual U15331EJ4V1UD (3) Cautions related to UART mode (a) When bit 7 (TXE20) of asynchronous ser

CHAPTER 11 SERIAL INTERFACE 20 User’s Manual U15331EJ4V1UD 211 11.4.3 3-wire serial I/O mode The 3-wire serial I/O mode is useful for conne

CHAPTER 11 SERIAL INTERFACE 20 212 User’s Manual U15331EJ4V1UD (b) Asynchronous serial interface mode register 20 (ASIM20) ASIM20 is set with

CHAPTER 11 SERIAL INTERFACE 20 User’s Manual U15331EJ4V1UD 213 (c) Baud rate generator control register 20 (BRGC20) BRGC20 is set with an 8

CHAPTER 11 SERIAL INTERFACE 20 214 User’s Manual U15331EJ4V1UD (2) Communication operation In 3-wire serial I/O mode, data transmission/recept

CHAPTER 11 SERIAL INTERFACE 20 User’s Manual U15331EJ4V1UD 215 Figure 11-11. 3-Wire Serial I/O Mode Timing (2/2) (ii) Slave operation timi

216 User’s Manual U15331EJ4V1UD CHAPTER 12 SERIAL INTERFACE 1A0 12.1 Function of Serial Interface 1A0 Serial interface 1A0 has the following t

CHAPTER 12 SERIAL INTERFACE 1A0 User’s Manual U15331EJ4V1UD 217 12.2 Configuration of Serial Interface 1A0 Serial interface 1A0 includes th

CHAPTER 12 SERIAL INTERFACE 1A0 218 User’s Manual U15331EJ4V1UD (1) Serial I/O shift register 1A0 (SIO1A0) This is an 8-bit register used to

CHAPTER 12 SERIAL INTERFACE 1A0 User’s Manual U15331EJ4V1UD 219 12.3 Control Registers for Serial Interface 1A0 Serial interface 1A0 is con

22 User’s Manual U15331EJ4V1UD LIST OF FIGURES (6/6) Figure No. Title Page 17-3 Releasing HALT Mode by RESET Input...

CHAPTER 12 SERIAL INTERFACE 1A0 220 User’s Manual U15331EJ4V1UD Figure 12-2. Format of Serial Operation Mode Register 1A0 Symbol <7> 6

CHAPTER 12 SERIAL INTERFACE 1A0 User’s Manual U15331EJ4V1UD 221 (2) Automatic data transmit/receive control register 0 (ADTC0) This registe

CHAPTER 12 SERIAL INTERFACE 1A0 222 User’s Manual U15331EJ4V1UD (3) Automatic data transmit/receive interval specification register 0 (ADTI0)

CHAPTER 12 SERIAL INTERFACE 1A0 User’s Manual U15331EJ4V1UD 223 Figure 12-4. Format of Automatic Data Transmit/Receive Interval Specificati

CHAPTER 12 SERIAL INTERFACE 1A0 224 User’s Manual U15331EJ4V1UD 12.4 Serial Interface 1A0 Operation Serial interface 1A0 provides the followi

CHAPTER 12 SERIAL INTERFACE 1A0 User’s Manual U15331EJ4V1UD 225 12.4.2 3-wire serial I/O mode The 3-wire serial I/O mode is useful for conn

CHAPTER 12 SERIAL INTERFACE 1A0 226 User’s Manual U15331EJ4V1UD Symbol <7> 6 <5> <4> 3 2 1 0 Address After reset R/W CSI

CHAPTER 12 SERIAL INTERFACE 1A0 User’s Manual U15331EJ4V1UD 227 (2) Communication operation In 3-wire serial I/O mode, data transmission/rec

CHAPTER 12 SERIAL INTERFACE 1A0 228 User’s Manual U15331EJ4V1UD Figure 12-5. 3-Wire Serial I/O Mode Timing (2/2) (ii) Slave operation timing

CHAPTER 12 SERIAL INTERFACE 1A0 User’s Manual U15331EJ4V1UD 229 (3) MSB/LSB switching as the start bit In the 3-wire serial I/O mode, trans

User’s Manual U15331EJ4V1UD 23 LIST OF TABLES (1/3) Table No. Title Page 2-1 Types of Pin I/O Circuits ...

CHAPTER 12 SERIAL INTERFACE 1A0 230 User’s Manual U15331EJ4V1UD 12.4.3 3-wire serial I/O mode with automatic transmit/receive function This 3

CHAPTER 12 SERIAL INTERFACE 1A0 User’s Manual U15331EJ4V1UD 231 Symbol <7> 6 <5> <4> 3 2 1 0 Address After reset R/W C

CHAPTER 12 SERIAL INTERFACE 1A0 232 User’s Manual U15331EJ4V1UD (b) Automatic data transmit/receive control register 0 (ADTC0) ADTC0 is set v

CHAPTER 12 SERIAL INTERFACE 1A0 User’s Manual U15331EJ4V1UD 233 (c) Automatic data transmit/receive interval specification register 0 (ADTI

CHAPTER 12 SERIAL INTERFACE 1A0 234 User’s Manual U15331EJ4V1UD Symbol <7> 6 5 <4> <3> <2> <1> <0> Add

CHAPTER 12 SERIAL INTERFACE 1A0 User’s Manual U15331EJ4V1UD 235 (2) Automatic transmit/receive data setting (a) Transmit data setting

CHAPTER 12 SERIAL INTERFACE 1A0 236 User’s Manual U15331EJ4V1UD (3) Communication operation (a) Basic transmit/receive mode This transmit/r

CHAPTER 12 SERIAL INTERFACE 1A0 User’s Manual U15331EJ4V1UD 237 Figure 12-8. Basic Transmit/Receive Mode Flowchart Remark ADTP0: Automa

CHAPTER 12 SERIAL INTERFACE 1A0 238 User’s Manual U15331EJ4V1UD In 6-byte transmission/reception (bit 6 (ARLD0) and bit 7 (RE0) of automatic d

CHAPTER 12 SERIAL INTERFACE 1A0 User’s Manual U15331EJ4V1UD 239 Figure 12-9. Buffer RAM Operation in 6-Byte Transmission/Reception

24 User’s Manual U15331EJ4V1UD LIST OF TABLES (2/3) Table No. Title Page 10-1 Configuration of 10-Bit A/D Converter ...

CHAPTER 12 SERIAL INTERFACE 1A0 240 User’s Manual U15331EJ4V1UD (b) Basic transmit mode In this mode, the specified number of 8-bit unit data

CHAPTER 12 SERIAL INTERFACE 1A0 User’s Manual U15331EJ4V1UD 241 Figure 12-11. Basic Transmit Mode Flowchart Remark ADTP0: Automatic dat

CHAPTER 12 SERIAL INTERFACE 1A0 242 User’s Manual U15331EJ4V1UD In 6-byte transmission (bit 6 (ARLD0) and bit 7 (RE0) of automatic data transm

CHAPTER 12 SERIAL INTERFACE 1A0 User’s Manual U15331EJ4V1UD 243 Figure 12-12. Buffer RAM Operation in 6-Byte Transmission (in Basic Transmi

CHAPTER 12 SERIAL INTERFACE 1A0 244 User’s Manual U15331EJ4V1UD (c) Repeat transmit mode In this mode, data stored in the buffer RAM is trans

CHAPTER 12 SERIAL INTERFACE 1A0 User’s Manual U15331EJ4V1UD 245 Figure 12-14. Repeat Transmit Mode Flowchart StartWrite transmit datain buf

CHAPTER 12 SERIAL INTERFACE 1A0 246 User’s Manual U15331EJ4V1UD In 6-byte transmission (bit 6 (ARLD0) and bit 7 (RE0) of automatic data transm

CHAPTER 12 SERIAL INTERFACE 1A0 User’s Manual U15331EJ4V1UD 247 Figure 12-15. Buffer RAM Operation in 6-Byte Transmission (in Repeat Transm

CHAPTER 12 SERIAL INTERFACE 1A0 248 User’s Manual U15331EJ4V1UD (d) Automatic transmission/reception suspension and restart Automatic transmi

CHAPTER 12 SERIAL INTERFACE 1A0 User’s Manual U15331EJ4V1UD 249 (4) Timing of interrupt request signal generation The interrupt request si

User’s Manual U15331EJ4V1UD 25 LIST OF TABLES (3/3) Table No. Title Page 21-1 Operand Identifiers and Description Methods ...

250 User’s Manual U15331EJ4V1UD CHAPTER 13 LCD CONTROLLER/DRIVER 13.1 LCD Controller/Driver Functions The functions of the LCD controller/dri

CHAPTER 13 LCD CONTROLLER/DRIVER User’s Manual U15331EJ4V1UD 251 The correspondence with the LCD display RAM is shown in Figure 13-1 below. Fi

CHAPTER 13 LCD CONTROLLER/DRIVER 252 User’s Manual U15331EJ4V1UD LCDC03 LCDC02LCDC01LCDC0022fLCD26fLCD27fLCD28fLCD29LCDON0VAON0VLC0COM0 COM1 COM

CHAPTER 13 LCD CONTROLLER/DRIVER User’s Manual U15331EJ4V1UD 253 13.3 Registers Controlling LCD Controller/Driver The LCD controller/driver is

CHAPTER 13 LCD CONTROLLER/DRIVER 254 User’s Manual U15331EJ4V1UD (1) LCD display mode register 0 (LCDM0) LCDM0 specifies whether to enable disp

CHAPTER 13 LCD CONTROLLER/DRIVER User’s Manual U15331EJ4V1UD 255 (2) LCD clock control register 0 (LCDC0) LCDC0 specifies the LCD source clock

CHAPTER 13 LCD CONTROLLER/DRIVER 256 User’s Manual U15331EJ4V1UD (3) LCD voltage boost control register 0 (LCDVA0) LCDVA0 controls the voltage

CHAPTER 13 LCD CONTROLLER/DRIVER User’s Manual U15331EJ4V1UD 257 13.4 Setting LCD Controller/Driver Set the LCD controller/driver using the fo

CHAPTER 13 LCD CONTROLLER/DRIVER 258 User’s Manual U15331EJ4V1UD 13.6 Common and Segment Signals Each pixel of the LCD panel turns on when the

CHAPTER 13 LCD CONTROLLER/DRIVER User’s Manual U15331EJ4V1UD 259 Figure 13-7. Common Signal Waveforms COMn(Three-time-slice mode)TF = 3 × TVLC

26 User’s Manual U15331EJ4V1UD CHAPTER 1 GENERAL 1.1 Features • ROM and RAM capacities Item Data Memory Part Number Program Memory (ROM) Int

CHAPTER 13 LCD CONTROLLER/DRIVER 260 User’s Manual U15331EJ4V1UD 13.7 Display Modes 13.7.1 Three-time-slice display example Figure 13-10 shows

CHAPTER 13 LCD CONTROLLER/DRIVER User’s Manual U15331EJ4V1UD 261 Figure 13-10. Example of Connecting Three-Time-Slice LCD Panel ××××××××××××××

CHAPTER 13 LCD CONTROLLER/DRIVER 262 User’s Manual U15331EJ4V1UD Figure 13-11. Three-Time-Slice LCD Drive Waveform Examples (1/3 Bias Method) V

CHAPTER 13 LCD CONTROLLER/DRIVER User’s Manual U15331EJ4V1UD 263 13.7.2 Four-time-slice display example Figure 13-13 shows how a 14-digit LCD

CHAPTER 13 LCD CONTROLLER/DRIVER 264 User’s Manual U15331EJ4V1UD Figure 13-13. Example of Connecting Four-Time-Slice LCD Panel 0010100010110010

CHAPTER 13 LCD CONTROLLER/DRIVER User’s Manual U15331EJ4V1UD 265 Figure 13-14. Four-Time-Slice LCD Drive Waveform Examples (1/3 Bias Method) T

CHAPTER 13 LCD CONTROLLER/DRIVER 266 User’s Manual U15331EJ4V1UD 13.8 Supplying LCD Drive Voltages VLC0, VLC1, and VLC2 The µPD789489 Subseries

User’s Manual U15331EJ4V1UD 267 CHAPTER 14 MULTIPLIER 14.1 Multiplier Function The multiplier has the following function. • Calculation of 8

CHAPTER 14 MULTIPLIER 268 User’s Manual U15331EJ4V1UD Figure 14-1. Block Diagram of Multiplier Internal busSelectorCounter value3CPU clockSta

CHAPTER 14 MULTIPLIER User’s Manual U15331EJ4V1UD 269 14.3 Multiplier Control Register The multiplier is controlled by the following register

CHAPTER 1 GENERAL User’s Manual U15331EJ4V1UD 27 1.3 Ordering Information Part Number Package Internal ROM µPD789488GC-×××-8BT 80-pin

CHAPTER 14 MULTIPLIER 270 User’s Manual U15331EJ4V1UD 14.4 Multiplier Operation The multiplier of the µPD789489 Subseries can execute the ca

User’s Manual U15331EJ4V1UD 271CHAPTER 15 REMOTE CONTROLLER RECEIVER (µPD789489, 78F9489 ONLY) 15.1 Remote Controller Receiver Functions The

CHAPTER 15 REMOTE CONTROLLER RECEIVER (µPD789489, 78F9489 ONLY) User’s Manual U15331EJ4V1UD 272 Figure 15-1. Block Diagram of Remote Controlle

CHAPTER 15 REMOTE CONTROLLER RECEIVER (µPD789489, 78F9489 ONLY) User’s Manual U15331EJ4V1UD 273(2) Remote controller receive data register (RM

CHAPTER 15 REMOTE CONTROLLER RECEIVER (µPD789489, 78F9489 ONLY) User’s Manual U15331EJ4V1UD 274 (4) Remote controller receive GPHS compare reg

CHAPTER 15 REMOTE CONTROLLER RECEIVER (µPD789489, 78F9489 ONLY) User’s Manual U15331EJ4V1UD 275(8) Remote controller receive DH0S compare regi

CHAPTER 15 REMOTE CONTROLLER RECEIVER (µPD789489, 78F9489 ONLY) User’s Manual U15331EJ4V1UD 276 (12) Remote controller receive end-width select

CHAPTER 15 REMOTE CONTROLLER RECEIVER (µPD789489, 78F9489 ONLY) User’s Manual U15331EJ4V1UD 27715.3 Registers to Control Remote Controller Rec

CHAPTER 15 REMOTE CONTROLLER RECEIVER (µPD789489, 78F9489 ONLY) User’s Manual U15331EJ4V1UD 278 Figure 15-3. Format of Remote Controller Recei

CHAPTER 15 REMOTE CONTROLLER RECEIVER (µPD789489, 78F9489 ONLY) User’s Manual U15331EJ4V1UD 27915.4 Operation of Remote Controller Receiver Th

CHAPTER 1 GENERAL 28 User’s Manual U15331EJ4V1UD 1.4 Pin Configuration (Top View) (1) µPD789488, 78F9488 80-pin plastic QFP (14 × 14) µPD78

CHAPTER 15 REMOTE CONTROLLER RECEIVER (µPD789489, 78F9489 ONLY) User’s Manual U15331EJ4V1UD 280 Figure 15-5. Operation Flow of Type A Receptio

CHAPTER 15 REMOTE CONTROLLER RECEIVER (µPD789489, 78F9489 ONLY) User’s Manual U15331EJ4V1UD 28115.4.3 Timing Operation varies depending on the

CHAPTER 15 REMOTE CONTROLLER RECEIVER (µPD789489, 78F9489 ONLY) User’s Manual U15331EJ4V1UD 282 (3) Data high level width determination Rela

CHAPTER 15 REMOTE CONTROLLER RECEIVER (µPD789489, 78F9489 ONLY) User’s Manual U15331EJ4V1UD 283(4) End width determination RINRMDLSRMDLL<1&

CHAPTER 15 REMOTE CONTROLLER RECEIVER (µPD789489, 78F9489 ONLY) User’s Manual U15331EJ4V1UD 284 Figure 15-6. Setting Example (Where n1 = 1, n2

CHAPTER 15 REMOTE CONTROLLER RECEIVER (µPD789489, 78F9489 ONLY) User’s Manual U15331EJ4V1UD 28515.4.5 Error interrupt generation timing After

CHAPTER 15 REMOTE CONTROLLER RECEIVER (µPD789489, 78F9489 ONLY) User’s Manual U15331EJ4V1UD 286 Figure 15-7. Generation Timing of INTRERR Sign

CHAPTER 15 REMOTE CONTROLLER RECEIVER (µPD789489, 78F9489 ONLY) User’s Manual U15331EJ4V1UD 28715.4.6 Noise elimination This remote controller

CHAPTER 15 REMOTE CONTROLLER RECEIVER (µPD789489, 78F9489 ONLY) User’s Manual U15331EJ4V1UD 288 Figure 15-8. Noise Elimination Operation Examp

CHAPTER 15 REMOTE CONTROLLER RECEIVER (µPD789489, 78F9489 ONLY) User’s Manual U15331EJ4V1UD 289Figure 15-8. Noise Elimination Operation Exampl

CHAPTER 1 GENERAL User’s Manual U15331EJ4V1UD 29 Cautions 1. Connect the IC (Internally Connected) pin directly to VSS. 2. Connect the A

290 User’s Manual U15331EJ4V1UD CHAPTER 16 INTERRUPT FUNCTIONS 16.1 Interrupt Function Types The following two types of interrupt functions a

CHAPTER 16 INTERRUPT FUNCTIONS User’s Manual U15331EJ4V1UD 291 Table 16-1. Interrupt Sources (µPD789488, 78F9488) Interrupt Source Interrupt

CHAPTER 16 INTERRUPT FUNCTIONS 292 User’s Manual U15331EJ4V1UD Table 16-2. Interrupt Sources (µPD789489, 78F9489) Interrupt Source Interrupt T

CHAPTER 16 INTERRUPT FUNCTIONS User’s Manual U15331EJ4V1UD 293 Figure 16-1. Basic Configuration of Interrupt Function (A) Internal non-mask

CHAPTER 16 INTERRUPT FUNCTIONS 294 User’s Manual U15331EJ4V1UD 16.3 Registers Controlling Interrupt Function The following five types of regis

CHAPTER 16 INTERRUPT FUNCTIONS User’s Manual U15331EJ4V1UD 295 (1) Interrupt request flag registers (IF0 to IF2) An interrupt request flag i

CHAPTER 16 INTERRUPT FUNCTIONS 296 User’s Manual U15331EJ4V1UD (2) Interrupt mask flag registers (MK0 to MK2) Interrupt mask flags are used to

CHAPTER 16 INTERRUPT FUNCTIONS User’s Manual U15331EJ4V1UD 297 (3) External interrupt mode registers (INTM0, INTM1) These registers are used

CHAPTER 16 INTERRUPT FUNCTIONS 298 User’s Manual U15331EJ4V1UD (4) Program status word (PSW) The program status word is used to hold the instr

CHAPTER 16 INTERRUPT FUNCTIONS User’s Manual U15331EJ4V1UD 299 (5) Key return mode register 00 (KRM00) This register is used to set the pin

User’s Manual U15331EJ4V1UD 3 1234VOLTAGE APPLICATION WAVEFORM AT INPUT PINWaveform distortion due to input noise or a reflected wave may cause ma

CHAPTER 1 GENERAL 30 User’s Manual U15331EJ4V1UD Notes 1. Whether to use these pins as input port pins (P70 to P73) or segment outputs (S16 to

CHAPTER 16 INTERRUPT FUNCTIONS 300 User’s Manual U15331EJ4V1UD (6) Key return mode register 01 (KRM01) (µPD789489, 78F9489 only) This register

CHAPTER 16 INTERRUPT FUNCTIONS User’s Manual U15331EJ4V1UD 301 16.4 Interrupt Servicing Operation 16.4.1 Non-maskable interrupt request ack

CHAPTER 16 INTERRUPT FUNCTIONS 302 User’s Manual U15331EJ4V1UD Figure 16-10. Flow from Generation of Non-Maskable Interrupt Request to Acknowl

CHAPTER 16 INTERRUPT FUNCTIONS User’s Manual U15331EJ4V1UD 303 16.4.2 Maskable interrupt request acknowledgment operation A maskable interru

CHAPTER 16 INTERRUPT FUNCTIONS 304 User’s Manual U15331EJ4V1UD Figure 16-14. Interrupt Request Acknowledgment Timing (Example: MOV A, r) Clock

CHAPTER 16 INTERRUPT FUNCTIONS User’s Manual U15331EJ4V1UD 305 Figure 16-16. Example of Multiple Interrupt Servicing Example 1. Acknowledg

CHAPTER 16 INTERRUPT FUNCTIONS 306 User’s Manual U15331EJ4V1UD 16.4.4 Putting interrupt requests on hold If an interrupt request (such as a ma

User’s Manual U15331EJ4V1UD 307 CHAPTER 17 STANDBY FUNCTION 17.1 Standby Function and Configuration 17.1.1 Standby function The standby fun

CHAPTER 17 STANDBY FUNCTION 308 User’s Manual U15331EJ4V1UD 17.1.2 Register controlling standby function The wait time after the STOP mode is r

CHAPTER 17 STANDBY FUNCTION User’s Manual U15331EJ4V1UD 309 17.2 Standby Function Operation 17.2.1 HALT mode (1) HALT mode The HALT mode is

CHAPTER 1 GENERAL User’s Manual U15331EJ4V1UD 31 1.5 78K/0S Series Lineup The products in the 78K/0S Series are listed below. The names encl

CHAPTER 17 STANDBY FUNCTION 310 User’s Manual U15331EJ4V1UD (2) Releasing HALT mode The HALT mode can be released by the following three sourc

CHAPTER 17 STANDBY FUNCTION User’s Manual U15331EJ4V1UD 311 (c) Release by RESET input When the HALT mode is released by the RESET signal, e

CHAPTER 17 STANDBY FUNCTION 312 User’s Manual U15331EJ4V1UD 17.2.2 STOP mode (1) Setting and operation status of STOP mode The STOP mode is

CHAPTER 17 STANDBY FUNCTION User’s Manual U15331EJ4V1UD 313 (2) Releasing STOP mode The STOP mode can be released by the following two sourc

CHAPTER 17 STANDBY FUNCTION 314 User’s Manual U15331EJ4V1UD (b) Release by RESET input When the STOP mode is released by the RESET signal, the

User’s Manual U15331EJ4V1UD 315 CHAPTER 18 RESET FUNCTION The following two operations are available to generate reset signals. (1) External

CHAPTER 18 RESET FUNCTION 316 User’s Manual U15331EJ4V1UD Figure 18-2. Reset Timing by RESET Input X1RESETInternalreset signalPort pinDuring n

CHAPTER 18 RESET FUNCTION User’s Manual U15331EJ4V1UD 317 Table 18-1. Status of Hardware After Reset (1/2) Hardware Status After Reset Progra

CHAPTER 18 RESET FUNCTION 318 User’s Manual U15331EJ4V1UD Table 18-1. Status of Hardware After Reset (2/2) Hardware Status After Reset Operat

User’s Manual U15331EJ4V1UD 319 CHAPTER 19 FLASH MEMORY VERSION The µPD78F9488 is available as the flash memory version of the µPD789488 (mas

CHAPTER 1 GENERAL 32 User’s Manual U15331EJ4V1UD The major functional differences between the subseries are listed below. Series for General-pu

CHAPTER 19 FLASH MEMORY VERSION 320 User’s Manual U15331EJ4V1UD 19.1 Flash Memory Characteristics Flash memory programming is performed by co

CHAPTER 19 FLASH MEMORY VERSION User’s Manual U15331EJ4V1UD 321 19.1.2 Communication mode Use the communication mode shown in Table 19-2 to

CHAPTER 19 FLASH MEMORY VERSION 322 User’s Manual U15331EJ4V1UD Figure 19-3. Example of Connection with Dedicated Flash Programmer (a) 3-wi

CHAPTER 19 FLASH MEMORY VERSION User’s Manual U15331EJ4V1UD 323 If Flashpro III/Flashpro IV is used as a dedicated flash programmer, the fol

CHAPTER 19 FLASH MEMORY VERSION 324 User’s Manual U15331EJ4V1UD 19.1.3 On-board pin processing When performing programming on the target syst

CHAPTER 19 FLASH MEMORY VERSION User’s Manual U15331EJ4V1UD 325 (1) Signal conflict If the dedicated flash programmer (output) is connected

CHAPTER 19 FLASH MEMORY VERSION 326 User’s Manual U15331EJ4V1UD <RESET pin> If the reset signal of the dedicated flash programmer is con

CHAPTER 19 FLASH MEMORY VERSION User’s Manual U15331EJ4V1UD 327 19.1.4 Connection of adapter for flash writing The following figure shows a

CHAPTER 19 FLASH MEMORY VERSION 328 User’s Manual U15331EJ4V1UD Figure 19-9. Wiring Example for Flash Writing Adapter with 3-Wire Serial I/O

CHAPTER 19 FLASH MEMORY VERSION User’s Manual U15331EJ4V1UD 329 Figure 19-10. Wiring Example for Flash Writing Adapter with UART GNDVDDSI

CHAPTER 1 GENERAL User’s Manual U15331EJ4V1UD 33 Series for ASSP Timer VDD Function Subseries Name ROM Capacity 8-Bit 16-Bit Watch WDT8-Bit

CHAPTER 19 FLASH MEMORY VERSION 330 User’s Manual U15331EJ4V1UD 19.2 Cautions on µPD78F9488 and 78F9489 (1) When using HALT mode with subclo

User’s Manual U15331EJ4V1UD 331 CHAPTER 20 MASK OPTIONS The µPD789488 and 789489 have the following mask options. • Pin function The segment

332 User’s Manual U15331EJ4V1UD CHAPTER 21 INSTRUCTION SET This chapter lists the instruction set of the µPD789489 Subseries. For details of t

CHAPTER 21 INSTRUCTION SET User’s Manual U15331EJ4V1UD 333 21.1.2 Description of “Operation” column A: A register; 8-bit accumulator X: X

CHAPTER 21 INSTRUCTION SET 334 User’s Manual U15331EJ4V1UD 21.2 Operation List Mnemonic Operands Bytes Clocks Operation Flag Z AC CYM

CHAPTER 21 INSTRUCTION SET User’s Manual U15331EJ4V1UD 335 Mnemonic Operands Bytes Clocks Operation Flag Z AC CYMOVW rp, #word 3 6 r

CHAPTER 21 INSTRUCTION SET 336 User’s Manual U15331EJ4V1UD Mnemonic Operands Bytes Clocks Operation Flag Z AC CYSUBC A, #byte 2 4

CHAPTER 21 INSTRUCTION SET User’s Manual U15331EJ4V1UD 337 Mnemonic Operands Bytes Clocks Operation Flag Z AC CYCMP A, #byte 2 4 A −

CHAPTER 21 INSTRUCTION SET 338 User’s Manual U15331EJ4V1UD Mnemonic Operands Bytes Clocks Operation Flag Z AC CYCALL !addr16 3 6 (SP −

CHAPTER 21 INSTRUCTION SET User’s Manual U15331EJ4V1UD 339 21.3 Instructions Listed by Addressing Type (1) 8-bit instructions MOV, XCH, ADD, A

CHAPTER 1 GENERAL 34 User’s Manual U15331EJ4V1UD 1.6 Block Diagram 78K/0SCPU coreROM(flashmemory)RAMVDDVSSIC0(VPP)CPT20/TO20/P338-bit timer/eve

CHAPTER 21 INSTRUCTION SET 340 User’s Manual U15331EJ4V1UD (2) 16-bit instructions MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW 2nd Ope

CHAPTER 21 INSTRUCTION SET User’s Manual U15331EJ4V1UD 341 (4) Call instructions/branch instructions CALL, CALLT, BR, BC, BNC, BZ, BNZ, DBNZ

342 User’s Manual U15331EJ4V1UD CHAPTER 22 ELECTRICAL SPECIFICATIONS (µPD789488, 78F9488, 789489, 78F9489) Absolute Maximum Ratings (TA = 25°

CHAPTER 22 ELECTRICAL SPECIFICATIONS (µPD789488, 78F9488, 789489, 78F9489) User’s Manual U15331EJ4V1UD 343 Caution Product quality may suf

CHAPTER 22 ELECTRICAL SPECIFICATIONS (µPD789488, 78F9488, 789489, 78F9489) 344 User’s Manual U15331EJ4V1UD Main System Clock Oscillator Chara

CHAPTER 22 ELECTRICAL SPECIFICATIONS (µPD789488, 78F9488, 789489, 78F9489) User’s Manual U15331EJ4V1UD 345 Subsystem Clock Oscillator Charac

CHAPTER 22 ELECTRICAL SPECIFICATIONS (µPD789488, 78F9488, 789489, 78F9489) 346 User’s Manual U15331EJ4V1UD DC Characteristics (TA = –40 to +8

CHAPTER 22 ELECTRICAL SPECIFICATIONS (µPD789488, 78F9488, 789489, 78F9489) User’s Manual U15331EJ4V1UD 347 DC Characteristics (TA = –40 to

CHAPTER 22 ELECTRICAL SPECIFICATIONS (µPD789488, 78F9488, 789489, 78F9489) 348 User’s Manual U15331EJ4V1UD DC Characteristics (TA = –40 to +8

CHAPTER 22 ELECTRICAL SPECIFICATIONS (µPD789488, 78F9488, 789489, 78F9489) User’s Manual U15331EJ4V1UD 349 DC Characteristics (TA = –40 to +

CHAPTER 1 GENERAL User’s Manual U15331EJ4V1UD 35 1.7 Overview of Functions (1/2) Item µPD789488 µPD78F9488 µPD789489 µPD78F9489 ROM 32 KB 3

CHAPTER 22 ELECTRICAL SPECIFICATIONS (µPD789488, 78F9488, 789489, 78F9489) 350 User’s Manual U15331EJ4V1UD DC Characteristics (TA = –40 to +8

CHAPTER 22 ELECTRICAL SPECIFICATIONS (µPD789488, 78F9488, 789489, 78F9489) User’s Manual U15331EJ4V1UD 351 DC Characteristics (TA = –40 to +

CHAPTER 22 ELECTRICAL SPECIFICATIONS (µPD789488, 78F9488, 789489, 78F9489) 352 User’s Manual U15331EJ4V1UD AC Characteristics (1) Basic op

CHAPTER 22 ELECTRICAL SPECIFICATIONS (µPD789488, 78F9488, 789489, 78F9489) User’s Manual U15331EJ4V1UD 353 (2) Serial interface 20 (SIO20)

CHAPTER 22 ELECTRICAL SPECIFICATIONS (µPD789488, 78F9488, 789489, 78F9489) 354 User’s Manual U15331EJ4V1UD (d) UART mode (external clock inp

CHAPTER 22 ELECTRICAL SPECIFICATIONS (µPD789488, 78F9488, 789489, 78F9489) User’s Manual U15331EJ4V1UD 355 (3) Serial interface 1A0 (SIO1A0

CHAPTER 22 ELECTRICAL SPECIFICATIONS (µPD789488, 78F9488, 789489, 78F9489) 356 User’s Manual U15331EJ4V1UD AC Timing Measurement Points (Excl

CHAPTER 22 ELECTRICAL SPECIFICATIONS (µPD789488, 78F9488, 789489, 78F9489) User’s Manual U15331EJ4V1UD 357 Key Return Input Timing tKRLKR0

CHAPTER 22 ELECTRICAL SPECIFICATIONS (µPD789488, 78F9488, 789489, 78F9489) 358 User’s Manual U15331EJ4V1UD 10-Bit A/D Converter Characteristi

CHAPTER 22 ELECTRICAL SPECIFICATIONS (µPD789488, 78F9488, 789489, 78F9489) User’s Manual U15331EJ4V1UD 359 LCD Characteristics (TA = –40 to

CHAPTER 1 GENERAL 36 User’s Manual U15331EJ4V1UD (2/2) Item µPD789488 µPD78F9488 µPD789489 µPD78F9489 Supply voltage VDD = 1.8 to 5.5 V Opera

CHAPTER 22 ELECTRICAL SPECIFICATIONS (µPD789488, 78F9488, 789489, 78F9489) 360 User’s Manual U15331EJ4V1UD Data Retention Timing (STOP Mode R

CHAPTER 22 ELECTRICAL SPECIFICATIONS (µPD789488, 78F9488, 789489, 78F9489) User’s Manual U15331EJ4V1UD 361 Flash Memory Writing and Erasing

362 User’s Manual U15331EJ4V1UD CHAPTER 23 CHARACTERISTICS CURVES OF LCD CONTROLLER/DRIVER (REFERENCE VALUES) (1) Characteristics curves of

CHAPTER 23 CHARACTERISTICS CURVES OF LCD CONTROLLER/DRIVER (REFERENCE VALUES) User’s Manual U15331EJ4V1UD 363 (2) Temperature characteri

364 User’s Manual U15331EJ4V1UD CHAPTER 24 PACKAGE DRAWINGS 80-PIN PLASTIC QFP (14x14)NOTEEach lead centerline is located within 0.13 mm ofits

CHAPTER 24 PACKAGE DRAWINGS User’s Manual U15331EJ4V1UD 365 80-PIN PLASTIC TQFP (FINE PITCH) (12x12)ITEM MILLIMETERSGH 0.22±0.051.25A 14.0±0.2C

366 User’s Manual U15331EJ4V1UD CHAPTER 25 RECOMMENDED SOLDERING CONDITIONS The µPD789489 subseries should be soldered and mounted under the f

CHAPTER 25 RECOMMENDED SOLDERING CONDITIONS User’s Manual U15331EJ4V1UD 367 Table 25-1. Surface Mounting Type Soldering Conditions (2/3) (3

CHAPTER 25 RECOMMENDED SOLDERING CONDITIONS 368 User’s Manual U15331EJ4V1UD Table 25-1. Surface Mounting Type Soldering Conditions (3/3) (

369 User’s Manual U15331EJ4V1UD APPENDIX A DEVELOPMENT TOOLS The following development tools are available for development of systems using th

User’s Manual U15331EJ4V1UD 37 CHAPTER 2 PIN FUNCTIONS 2.1 List of Pin Functions (1) Port pins (1/2) Pin Name I/O Function After Reset

APPENDIX A DEVELOPMENT TOOLS User’s Manual U15331EJ4V1UD 370 Figure A-1. Development Tools Language processing software· Assembler package· C

APPENDIX A DEVELOPMENT TOOLS User’s Manual U15331EJ4V1UD 371 A.1 Software Package Software tools for development of the 78K/0S Series are comb

APPENDIX A DEVELOPMENT TOOLS 372 User’s Manual U15331EJ4V1UD Remark ×××× in the part number differs depending on the host machine and operating

APPENDIX A DEVELOPMENT TOOLS User’s Manual U15331EJ4V1UD 373 A.5 Debugging Tools (Hardware) IE-78K0S-NS In-circuit emulator In-circuit emulato

APPENDIX A DEVELOPMENT TOOLS 374 User’s Manual U15331EJ4V1UD A.6 Debugging Tools (Software) This debugger supports the in-circuit emulators IE-

User’s Manual U15331EJ4V1UD 375APPENDIX B NOTES ON TARGET SYSTEM DESIGN Figures B-1 to B-6 show the conditions when connecting the emulation

APPENDIX B NOTES ON TARGET SYSTEM DESIGN User’s Manual U15331EJ4V1UD 376 Figure B-2. Connection Conditions of Target System (When NP-80GC-TQ

APPENDIX B NOTES ON TARGET SYSTEM DESIGN User’s Manual U15331EJ4V1UD 377(2) NP-80GK, NP-H80GK-TQ Figure B-4. Distance Between In-Circuit Em

APPENDIX B NOTES ON TARGET SYSTEM DESIGN User’s Manual U15331EJ4V1UD 378 Figure B-5. Connection Conditions of Target System (When NP-80GK Is

379 User’s Manual U15331EJ4V1UD APPENDIX C REGISTER INDEX C.1 Register Index (Register Names in Alphabetic Order) [A] A/D conversion result r

CHAPTER 2 PIN FUNCTIONS User’s Manual U15331EJ4V1UD 38 (1) Port pins (2/2) Pin Name I/O Function After Reset Alternate Function P70 to P7

APPENDIX C REGISTER INDEX 380 User’s Manual U15331EJ4V1UD [L] LCD clock control register 0 (LCDC0) ...

APPENDIX C REGISTER INDEX User’s Manual U15331EJ4V1UD 381 Remote controller receive end width select register (RMER) ...

APPENDIX C REGISTER INDEX 382 User’s Manual U15331EJ4V1UD C.2 Register Index (Register Symbols Alphabetic Order) [A] ADCRL0: A/D conversion re

APPENDIX C REGISTER INDEX User’s Manual U15331EJ4V1UD 383 MUL0H: 16-bit multiplication result storage register H...

APPENDIX C REGISTER INDEX 384 User’s Manual U15331EJ4V1UD SIO1A0: Serial I/O shift register 1A0...

User’s Manual U15331EJ4V1UD 385APPENDIX D REVISION HISTORY The following table shows the revision history up to this edition. The “Applied to:

APPENDIX D REVISION HISTORY User’s Manual U15331EJ4V1UD 386 (2/4) Edition Major Revision from Previous Edition Applied to: Addition of desc

APPENDIX D REVISION HISTORY User’s Manual U15331EJ4V1UD 387(3/4) Edition Major Revision from Previous Edition Applied to: Change of descripti

APPENDIX D REVISION HISTORY User’s Manual U15331EJ4V1UD 388 (4/4) Edition Major Revision from Previous Edition Applied to: Modification of d

CHAPTER 2 PIN FUNCTIONS User’s Manual U15331EJ4V1UD 39(2) Non-port pins (2/2) Pin Name I/O Function After Reset Alternate Function S0 to

4 User’s Manual U15331EJ4V1UD EEPROM and FIP are trademarks of NEC Electronics Corporation. Windows and Windows NT are either registered trademarks

CHAPTER 2 PIN FUNCTIONS User’s Manual U15331EJ4V1UD 40 2.2 Description of Pin Functions 2.2.1 P00 to P07 (Port 0) These pins constitute an 8

CHAPTER 2 PIN FUNCTIONS User’s Manual U15331EJ4V1UD 412.2.4 P30 to P34 (Port 3) These pins constitute a 5-bit I/O port. In addition, they al

CHAPTER 2 PIN FUNCTIONS User’s Manual U15331EJ4V1UD 42 2.2.6 P60 to P67 (Port 6) This is an 8-bit input-only port. In addition to a general-p

CHAPTER 2 PIN FUNCTIONS User’s Manual U15331EJ4V1UD 432.2.13 RESET This pin inputs an active-low system reset signal. 2.2.14 X1, X2 These p

CHAPTER 2 PIN FUNCTIONS User’s Manual U15331EJ4V1UD 44 2.2.21 IC0 (mask ROM version only) The IC0 (Internally Connected) pin is used to set t

CHAPTER 2 PIN FUNCTIONS User’s Manual U15331EJ4V1UD 452.3 Pin I/O Circuits and Recommended Connection of Unused Pins The I/O circuit type of

CHAPTER 2 PIN FUNCTIONS User’s Manual U15331EJ4V1UD 46 Table 2-1. Types of Pin I/O Circuits (2/2) Pin Name I/O Circuit Type I/O Recommende

CHAPTER 2 PIN FUNCTIONS User’s Manual U15331EJ4V1UD 47Figure 2-1. I/O Circuit Types (2/2) Type 13-W Type 13-V DataOutputdisableInputenab

48 User’s Manual U15331EJ4V1UD CHAPTER 3 CPU ARCHITECTURE 3.1 Memory Space The µPD789489 Subseries can access 64 KB of memory space. Figures

CHAPTER 3 CPU ARCHITECTURE User’s Manual U15331EJ4V1UD 49 Figure 3-2. Memory Map (µPD78F9488) 8 0 0 0 H7 F F F HSpecial function registers256

User’s Manual U15331EJ4V1UD 5 The information in this document is current as of July, 2005. The information is subject to change withou

CHAPTER 3 CPU ARCHITECTURE 50 User’s Manual U15331EJ4V1UD Figure 3-3. Memory Map (µPD789489) B F F F H0 0 0 0 H0 0 8 0 H0 0 7 F H0 0 4 0 H0 0 3

CHAPTER 3 CPU ARCHITECTURE User’s Manual U15331EJ4V1UD 51 Figure 3-4. Memory Map (µPD78F9489) B F F F H0 0 0 0 H0 0 8 0 H0 0 7 F H0 0 4 0 H0 0

CHAPTER 3 CPU ARCHITECTURE 52 User’s Manual U15331EJ4V1UD 3.1.1 Internal program memory space The internal program memory space stores programs

CHAPTER 3 CPU ARCHITECTURE User’s Manual U15331EJ4V1UD 53 3.1.2 Internal data memory space (1) Internal high-speed RAM and internal low-speed

CHAPTER 3 CPU ARCHITECTURE 54 User’s Manual U15331EJ4V1UD 3.1.4 Data memory addressing The µPD789489 Subseries is provided with a variety of ad

CHAPTER 3 CPU ARCHITECTURE User’s Manual U15331EJ4V1UD 55 Figure 3-6. Data Memory Addressing (µPD78F9488) Special function registers256 × 8 bi

CHAPTER 3 CPU ARCHITECTURE 56 User’s Manual U15331EJ4V1UD Figure 3-7. Data Memory Addressing (µPD789489) Direct addressingRegister indirect add

CHAPTER 3 CPU ARCHITECTURE User’s Manual U15331EJ4V1UD 57 Figure 3-8. Data Memory Addressing (µPD78F9489) Direct addressingRegister indirect a

CHAPTER 3 CPU ARCHITECTURE 58 User’s Manual U15331EJ4V1UD 3.2 Processor Registers The µPD789489 Subseries is provided with the following on-chi

CHAPTER 3 CPU ARCHITECTURE User’s Manual U15331EJ4V1UD 59 (a) Interrupt enable flag (IE) This flag controls interrupt request acknowledgement

6 User’s Manual U15331EJ4V1UD Regional Information• Device availability• Ordering information• Product release schedule• Availability of relat

CHAPTER 3 CPU ARCHITECTURE 60 User’s Manual U15331EJ4V1UD (3) Stack pointer (SP) This is a 16-bit register that holds the start address of the

CHAPTER 3 CPU ARCHITECTURE User’s Manual U15331EJ4V1UD 61 3.2.2 General-purpose registers The general-purpose registers consist of eight 8-bit

CHAPTER 3 CPU ARCHITECTURE 62 User’s Manual U15331EJ4V1UD 3.2.3 Special function registers (SFRs) Unlike a general-purpose register, each speci

CHAPTER 3 CPU ARCHITECTURE User’s Manual U15331EJ4V1UD 63 Table 3-4. Special Function Registers (1/3) Bit Unit for ManipulationAddress Specia

CHAPTER 3 CPU ARCHITECTURE 64 User’s Manual U15331EJ4V1UD Table 3-4. Special Function Registers (2/3) Bit Unit for Manipulation Address Specia

CHAPTER 3 CPU ARCHITECTURE User’s Manual U15331EJ4V1UD 65 Table 3-4. Special Function Registers (3/3) Bit Unit for ManipulationAddress Specia

CHAPTER 3 CPU ARCHITECTURE 66 User’s Manual U15331EJ4V1UD 3.3 Instruction Address Addressing An instruction address is determined by the progra

CHAPTER 3 CPU ARCHITECTURE User’s Manual U15331EJ4V1UD 67 3.3.2 Immediate addressing [Function] Immediate data in the instruction word is tran

CHAPTER 3 CPU ARCHITECTURE 68 User’s Manual U15331EJ4V1UD 3.3.3 Table indirect addressing [Function] Table contents (branch destination address

CHAPTER 3 CPU ARCHITECTURE User’s Manual U15331EJ4V1UD 69 3.4 Operand Address Addressing The following various methods are available to specif

User’s Manual U15331EJ4V1UD 7 Major Revisions in This Edition Page Description Throughout Change of descriptions of µPD789489, 78F9489 • Change o

CHAPTER 3 CPU ARCHITECTURE 70 User’s Manual U15331EJ4V1UD 3.4.2 Short direct addressing [Function] The memory to be manipulated in the fixed sp

CHAPTER 3 CPU ARCHITECTURE User’s Manual U15331EJ4V1UD 71 3.4.3 Special function register (SFR) addressing [Function] The memory-mapped specia

CHAPTER 3 CPU ARCHITECTURE 72 User’s Manual U15331EJ4V1UD 3.4.4 Register addressing [Function] In the register addressing mode, general-purpose

CHAPTER 3 CPU ARCHITECTURE User’s Manual U15331EJ4V1UD 73 3.4.5 Register indirect addressing [Function] In the register indirect addressing mo

CHAPTER 3 CPU ARCHITECTURE 74 User’s Manual U15331EJ4V1UD 3.4.6 Based addressing [Function] 8-bit immediate data is added to the contents of th

User’s Manual U15331EJ4V1UD 75 CHAPTER 4 PORT FUNCTIONS 4.1 Port Functions The µPD789489 Subseries provides the ports shown in Figure 4-1,

CHAPTER 4 PORT FUNCTIONS 76 User’s Manual U15331EJ4V1UD Table 4-1. Port Functions Port Name Pin Name Function Port 0 P00 to P07 I/O port.

CHAPTER 4 PORT FUNCTIONS User’s Manual U15331EJ4V1UD 77 4.2.1 Port 0 This is an 8-bit I/O port with an output latch. Port 0 can be specified

CHAPTER 4 PORT FUNCTIONS 78 User’s Manual U15331EJ4V1UD 4.2.2 Port 1 This is a 2-bit I/O port with an output latch. Port 1 can be specified in

CHAPTER 4 PORT FUNCTIONS User’s Manual U15331EJ4V1UD 79 4.2.3 Port 2 This is a 6-bit I/O port with an output latch. Port 2 can be specified i

8 User’s Manual U15331EJ4V1UD INTRODUCTION Target Readers This manual is intended for user engineers who wish to understand the functions of the µP

CHAPTER 4 PORT FUNCTIONS 80 User’s Manual U15331EJ4V1UD Figure 4-5. Block Diagram of P21 Internal busVDDP21/SO20/TxD20WRPUB2RDWRPORTWRPMPUB21Al

CHAPTER 4 PORT FUNCTIONS User’s Manual U15331EJ4V1UD 81 Figure 4-6. Block Diagram of P22 and P25 P22/SI20/RxD20,P25/SI10WRPUB2RDWRPORTWRPMPUB2

CHAPTER 4 PORT FUNCTIONS 82 User’s Manual U15331EJ4V1UD Figure 4-7. Block Diagram of P23 Internal busVDDP-chP23/SCK10WRPUB2RDWRPORTWRPMPUB23Alt

CHAPTER 4 PORT FUNCTIONS User’s Manual U15331EJ4V1UD 83 Figure 4-8. Block Diagram of P24 Internal busVDDP24/SO10WRPUB2RDWRPORTWRPMPUB24Alterna

CHAPTER 4 PORT FUNCTIONS 84 User’s Manual U15331EJ4V1UD 4.2.4 Port 3 This is a 5-bit I/O port with an output latch. Port 3 can be specified in

CHAPTER 4 PORT FUNCTIONS User’s Manual U15331EJ4V1UD 85 Figure 4-10. Block Diagram of P34 (a) When µPD789488, 78F9488 is used P34WRPUB3RDWRPO

CHAPTER 4 PORT FUNCTIONS 86 User’s Manual U15331EJ4V1UD 4.2.5 Port 5 This is a 4-bit N-ch open-drain I/O port with an output latch. Port 5 can

CHAPTER 4 PORT FUNCTIONS User’s Manual U15331EJ4V1UD 87 4.2.6 Port 6 This is an 8-bit input-only port. This port is also used for the analog

CHAPTER 4 PORT FUNCTIONS 88 User’s Manual U15331EJ4V1UD Figure 4-12. Block Diagram of P60 to P67 (2/2) (b) When µPD789489, 78F9489 is used VRE

CHAPTER 4 PORT FUNCTIONS User’s Manual U15331EJ4V1UD 89 4.2.7 Port 7 This is a 4-bit input-only port. Only the bits for which the port funct

User’s Manual U15331EJ4V1UD 9 Conventions Data significance: Higher digits on the left and lower digits on the right Active low representation:

CHAPTER 4 PORT FUNCTIONS 90 User’s Manual U15331EJ4V1UD 4.2.8 Port 8 This is an 8-bit I/O port with an output latch. Only the bits for which th

CHAPTER 4 PORT FUNCTIONS User’s Manual U15331EJ4V1UD 91 4.3 Registers Controlling Port Function The ports are controlled by the following thre

CHAPTER 4 PORT FUNCTIONS 92 User’s Manual U15331EJ4V1UD Table 4-3. Port Mode Registers and Output Latch Settings When Using Alternate Functions

CHAPTER 4 PORT FUNCTIONS User’s Manual U15331EJ4V1UD 93 (2) Pull-up resistor option registers (PUB0 to PUB3) These registers set whether to us

CHAPTER 4 PORT FUNCTIONS 94 User’s Manual U15331EJ4V1UD 4.4 Port Function Operation The operation of a port differs depending on whether the p

User’s Manual U15331EJ4V1UD 95 CHAPTER 5 CLOCK GENERATOR 5.1 Clock Generator Functions The clock generator generates the clock to be supplied

CHAPTER 5 CLOCK GENERATOR 96 User’s Manual U15331EJ4V1UD Figure 5-1. Clock Generator Block Diagram (µPD789488, 789489) fXT8fXTfXTTX1X2XT1XT2fX

CHAPTER 5 CLOCK GENERATOR User’s Manual U15331EJ4V1UD 97 Figure 5-2. Clock Generator Block Diagram (µPD78F9488, 78F9489) Subsystemclock oscill

CHAPTER 5 CLOCK GENERATOR 98 User’s Manual U15331EJ4V1UD 5.3 Registers Controlling Clock Generator The clock generator is controlled by the fol

CHAPTER 5 CLOCK GENERATOR User’s Manual U15331EJ4V1UD 99 (2) Subclock oscillation mode register (SCKM) SCKM selects a feedback resistor for the