NEC PD75P402 User Manual

USER'S MANUALµPD75402A4-BIT SINGLE-CHIP MICROCOMPUTERµPD75402AµPD75P402Document No. IEU1270C(O. D. No. IEU-644D)Date Published March 1994 PP

- v -Fig. No. Title Page5-32 Example of SBI Serial Bus System Configuration ...

89CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS(3) Serial clock selectionSerial clock selection is performed by setting bit 1 of the serial operating m

90CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS(5) Data transfer orderThe µPD75402A 3-wire serial I/O mode differs from that of other 75X series produc

91CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS(7) 3-wire serial I/O mode applications(a) To transfer data MSB-first (master operation) using a 262 kHz

92CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS(b) To transmit/receive MSB-first data using an external clock (slave operation).➤➤➤P01/SCKµPD75402ASISO

93CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS5.5.6 SBI Mode OperationThe SBI (serial bus interface) is a high-speed serial interface which conforms t

94CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS(1) SBI functionsSince conventional serial I/O methods have only data transfer functions, when a serial

95CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS(2) SBI definitionThe SBI serial data format and the meaning of the signals used are explained in the fo

96CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONSSCKSB0“H”The bus release signal indicates that the master is about to send an address to a slave. Sla

97CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS(c) AddressAn address is 8-bit data output by the master to slaves connected to the bus line in order to

98CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS(d) Command & dataThe master performs command transmission to or data transmission/reception to/from

- vi -CONTENTS OF TABLESTable No. Title Page1-1 Differences Between µPD75402A and µPD75402, 75P402 ...

99CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS(e) Acknowledge signal (ACK)The acknowledge signal is used to confirm serial data reception between the

100CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS(f) Busy signal (BUSY), ready signal (READY)The busy signal notifies the master that a slave is prepari

101CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS(3) Register settingWhen the device is used in the SBI mode, setting can be performed by means of the f

102CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONSWake-up function specification bit (W)IRQCSI set at end of every serial transfer in SBI mode mask state

103CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS(b) Serial bus interface control register (SBIC)When the SBI mode is used, SBIC is set as shown below (

104CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONSBus release detection flag (R)Clearing Conditions (RELD = 0) Setting Condition (RELD = 1)➀ When a trans

105CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONSBusy enable bit (R/W)0➀ Disablin of automatic busy signal output➁ Busy signal output is stopped in sync

106CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS(5) SignalsThe operation of signals and flags in SBIC in the SBI mode are shown in Figs. 5-42 to 5-47,

107CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONSFig. 5-44 ACKT OperationNote ACKT must not be set before the end of a transfer.SCKSB0ACKTWhen set

108CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONSFig. 5-45 ACKE Operation(a) When ACKE = 1 on completion of transfer(b) When ACKE is set after completi

1CHAPTER 1. GENERALName Program Memory Data MemoryµPD75402A 1920 × 8 (mask ROM) 64 × 4 (RAM)µPD75P402 1920 × 8 (one-time PROM) 64 × 4 (RAM)CHAPTER

109CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONSFig. 5-46 ACKD Operation(a) When ACK signal is output in 9th SCK clock interval(b) When ACK signal is

110CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONSTable 5-8 Signals in SBI Mode (1/2)Signal NameOutputDeviceTiming ChartDefinitionOutputConditionEffect

111CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONSTable 5-8 Signals in SBI Mode (2/2)Signal NameOutputDeviceTiming ChartDefinitionOutputConditionEffect

112CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS(6) Pin configurationThe configuration of the serial clock pin (SCK) and the serial data bus pin SB0 is

113CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS(7) Address match detection methodIn the SBI mode, master address communication is used to select a spe

114CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONSFig. 5-49 Address Transmission form Master Device to Slave Device (WUP = 1)RELTSettingCMDTSettingS

115CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONSFig. 5-50 Command Transmission from Master Device to Slave DeviceIRQCSIGenera-tionACKDSettingSCK

116CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONSFig. 5-51 Data Transmission from Master Device to Slave DeviceProgramProcessingHardwareOperationMa

117CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONSFig. 5-52 Data Transmission from Slave Device to Master Device★Master Device Processing (Reception Si

118CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS(10) Start of transferWhen the following two conditions are met a serial transfer is started by setting

2CHAPTER 1. GENERALItem Description1.1 OUTLINE OF FUNCTIONSNumber of basicinstructionsInstructionexecution timeBuilt-inmemoryGeneral registerAccumul

119CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONSVDDSB0 (SB1)SCKSB0 (SB1)SCKSB0 SCKSB0 (SB1)SCK(12) SBI mode applicationThis section presents e

120CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS(b) Description of commands(i) Command typesThe following command types are used in these application e

121CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONSRemarks M : Output by masterS : Output by slaveAfter the slave receives the data length, if the transmi

122CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONSAfter the slave receives the data length, if the area for storing the receive data is at least as large

123CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS➂ STATUS commandThis command is used to read the status of the currently selected slave.Fig. 5-57 STAT

124CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONSRESET commandThis command is used to change the currently selected slave to non-selected status. All sl

125CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS(iv) Error occurrenceOperation in the event of an error in communication is described below.A slave ind

126CHAPTER 6. INTERRUPT FUNCTIONSCHAPTER 6. INTERRUPT FUNCTIONSOn the µPD75402A there are 3 vectored interrupt sources and one testable input, e

127CHAPTER 6. INTERRUPT FUNCTIONSFig. 6-1 Interrupt Control Circuit Block DiagramInternal Bus3IM0Sampling Clock Noise EliminationCircuitAnal

128CHAPTER 6. INTERRUPT FUNCTIONS6.2 INTERRUPT SOURCE TYPES AND VECTOR TABLEThe µPD75402A’s interrupt source types and interrupt vector table are s

3CHAPTER 1. GENERALOrdering Code Package Program MemoryµPD75402AC-××× 28-pin plastic DIP (600 mil) Mask ROMµPD75402ACT-××× 28-pin plastic shrink DIP

129CHAPTER 6. INTERRUPT FUNCTIONSInterrupt Request FlagIRQBTIRQ0IRQCSIIRQ26.3 INTERRUPT CONTROL CIRCUIT HARDWARE(1) Interrupt request flag & in

130CHAPTER 6. INTERRUPT FUNCTIONS(2) External interrupt input pin hardwareThe configuration of INT0 and INT2 is shown in Fig. 6-3.Fig. 6-3 Configur

131CHAPTER 6. INTERRUPT FUNCTIONSFig. 6-4 INT0 Noise Elimination Circuit Input/Output TimingRemarks tSMP = tCY or 64/fXXSpecification of the detect

132CHAPTER 6. INTERRUPT FUNCTIONSThe format of the edge detection mode register (IM0) which is used to select the detected edge is shown in Fig.6-6

133CHAPTER 6. INTERRUPT FUNCTIONS(4) Interrupt status flagThe interrupt status flag (IST0) is the flag which shows the status of the processing cur

134CHAPTER 6. INTERRUPT FUNCTIONS6.4 INTERRUPT SEQUENCEWhen an interrupt is generated, it is serviced by the procedure shown in Fig. 6-8.Fig. 6-8 I

135CHAPTER 6. INTERRUPT FUNCTIONS6.5 MACHINE CYCLES BEFORE INTERRUPT SERVICINGOn the 75X, the machine cycles from the setting of the interrupt requ

136CHAPTER 6. INTERRUPT FUNCTIONS(2) When IRQn is set during execution of an instruction other than an interrupt control instruction(a) When IRQn i

137CHAPTER 6. INTERRUPT FUNCTIONS6.6 INTERRUPT APPLICATIONSWhen the interrupt function is used, the following setting are first carried out in the

138CHAPTER 6. INTERRUPT FUNCTIONS(2) Example using INTBT, INT0 (falling edge active), and INTCSI➀ Reset➁ MOVMOVCLR1➂ EIEIEIEI➄ RETI&

4CHAPTER 1. GENERALInstructionexecution timePort 5’s pull-up resistorSupply voltageOperatingtemperature rangePackage1.3 DIFFERENCES BETWEEN µPD75402

139CHAPTER 6. INTERRUPT FUNCTIONS(3) Pending interrupt execution - interrupt input in interrupt disabled stateReset➂ INTCSI<INT0 Service Prog

140CHAPTER 6. INTERRUPT FUNCTIONS(4) Pending interrupt executionResetEIEIEI➀ IECSIIE0<Main Program>INT0INTCSIRETI➁ RETI<I

141CHAPTER 7. STANDBY FUNCTIONCHAPTER 7. STANDBY FUNCTIONThe µPD75402A has a standby function which can reduce the system power consumption. The

142CHAPTER 7. STANDBY FUNCTION7.1 STANDBY MODE SETTING AND OPERATION STATESTable 7-1 Standby Mode Operation StatesSTOP Mode HALT ModeSetting instr

143CHAPTER 7. STANDBY FUNCTION7.2 STANDBY MODE RESETThe STOP mode is reset only by RESET input. The HALT mode is reset by standby release signal by

144CHAPTER 7. STANDBY FUNCTIONFig. 7-1 Standby Mode Reset Operation(a) STOP mode reset by RESET input(b) HALT mode reset by RESET inputHALTInstru

145CHAPTER 7. STANDBY FUNCTION7.3 OPERATION AFTER STANDBY MODE RESET(1) When the standby mode was reset by RESET input, normal reset operation is e

146CHAPTER 8. RESET FUNCTIONCHAPTER 8. RESET FUNCTIONWhen low level is input to the RESET pin, system reset is applied and the hardware enters t

147CHAPTER 8. RESET FUNCTIONTable 8-1 State of Hardware after Reset* The contents of data memory addresses 038H to 03DH are made undefined by RESE

148CHAPTER 9. INSTRUCTION SETCHAPTER 9. INSTRUCTION SETThe 75X series instruction set is an improved and expanded version of old µPD7500 series

5CHAPTER 1. GENERALBASICINTERVALTIMERSERIALINTERFACEINTERRUPTCONTROLINTBTINTCSISISO/SB0SCKINT0INT2PROGRAMCOUNTER(11)ROM (PROM)PRO

149CHAPTER 9. INSTRUCTION SET9.1 SPECIAL INSTRUCTIONSThis section outlines the special instructions of the µPD75402A instruction set.9.1.1 Bit Man

150CHAPTER 9. INSTRUCTION SET9.1.3 Base Correction InstructionsDepending on the application, the result of addition of 4-bit data must be converted

151CHAPTER 9. INSTRUCTION SET9.2 INSTRUCTION SET AND ITS OPERATION(1) Operation identifier and descriptionThe operands are described in the operand

152CHAPTER 9. INSTRUCTION SET(3) Description of addressing area field symbols* 1 MB = 0* 2 MB = 0 (00H to 3FH)MB = 15 (80H to FFH)* 3 MB = 15, fm

153CHAPTER 9. INSTRUCTION SETA, #n 4 1 1 A ← n 4 Stack AXA, #n 8 2 2 XA ← n 8 Stack AHL, #n 8 2 2 HL ← n 8 Stack BA, @HL 1 1 A ← (HL) *1MOV @HL, A

154CHAPTER 9. INSTRUCTION SETmem. bit 2 2 (mem. bit) ← 1*2f mem. bit 2 2 (f mem.bit) ← 1*3mem. bit 2 2 (mem. bit) ← 0*2f mem. bit 2 2 (f mem. bit)

155CHAPTER 9. INSTRUCTION SETIN A, PORTn 2 2 A ← PORTn (n = 0 – 3, 5, 6)OUT PORTn, A 2 2 PORTn ← A (n + 2, 3, 5, 6)HALT 2 2 Set HALT Mode (PCC.2 ←

156CHAPTER 9. INSTRUCTION SETR1 R0 reg00A01X10 L11H9.3 OPERATION CODE OF EACH INSTRUCTION(1) Description of operation code symbolsP1 reg-pair0XA1HL

157CHAPTER 9. INSTRUCTION SETOperation CodeB1 B2XCHMOVNote 1. Instruction Group2. Accumulator operation instructions3. Increment/decrement instruct

158CHAPTER 9. INSTRUCTION SETmem. bitf mem. bitmem. bitf mem. bitmem. bitf mem. bitmem. bitf mem. bitSKTCLR f mem. bitAND 1 CY, f mem. bitOR 1 CY,

6CHAPTER 1. GENERAL1.5 PIN CONFIGURATION1.5.1 28-Pin Plastic Dip (600 mil), Shrink Dip (400 mil)(1) Normal operating modeP00 to P03 : Port 0 SCK :

159CHAPTER 9. INSTRUCTION SET9.4 INSTRUCTION FUNCTIONS AND APPLICATION9.4.1 Move InstructionsMOV A, #n4Function: A ← n4; n4 = I3 to I0 : 0 to FHMo

160CHAPTER 9. INSTRUCTION SETMOV @HL, AFunction: (HL) ← AMoves the contents of the A register to the data memory addressed by the contents of regis

161CHAPTER 9. INSTRUCTION SETXCH A, @HLFunction: A ← (HL)Exchanges the contents of the A register and the contents of the data memory addressed by

162CHAPTER 9. INSTRUCTION SET9.4.2 Table Reference InstructionsMOVT XA, @PCXAFunction: XA ← ROM (PC10 to PC8 + XA)Moves the high-order three bits (

163CHAPTER 9. INSTRUCTION SET9.4.3 Arithmetic and Logic InstructionsADDS A, #n4Function: A ← A + n4; Skip if carry; n4 = I3 to I0 : 0 to FHBinary a

164CHAPTER 9. INSTRUCTION SETOR A, @HLFunction: A ← A ∨ (HL)ORs the contents of the A register and the data memory contents addressed by register

165CHAPTER 9. INSTRUCTION SET9.4.4 Accumulator Operation InstructionsRORC AFunction: CY ← A0 An to A1 ← An , A3 ← CY (n = 1 to 3)Rotates the conte

166CHAPTER 9. INSTRUCTION SET9.4.5 Increment/Decrement InstructionsINCS regFunction: reg ← reg + 1; Skip if reg = 0Increments the contents of regi

167CHAPTER 9. INSTRUCTION SET9.4.6 Compare InstructionsSKE reg, #n4Function: Skip if reg = n4; n4 = I3 to I0 : 0 to FHIf the contents of register r

168CHAPTER 9. INSTRUCTION SET9.4.7 Carry Flag Operation InstructionsSET1 CYFunction: CY ← 1Sets the carry flag.CLR1 CYFunction: CY ← 0Clears the ca

7CHAPTER 1. GENERAL(2) PROM modeA0 to A14 : Address inputO0 to O7 : Data input/outputCE : Chip enable inputOE : Output enable inputVDD : Power suppl

169CHAPTER 9. INSTRUCTION SET9.4.8 Bit Manipuration InstructionsSET1 mem. bitFunction: (mem. bit) ← 1; mem = D7 to D0 : 00H to 3FH, bit = B1 to B0

170CHAPTER 9. INSTRUCTION SETSKF mem. bitFunction: Skit if (mem. bit) = 0; mem = D7 to D0 : 00H to 3FH, bit = B1 to B0 : 0 to 3If the bit specified

171CHAPTER 9. INSTRUCTION SET9.4.9 Branch InstructionsBR addrFunction: PC10 to PC0 ← addr; addr = 000H to 77FHBranches to the address addressed by

172CHAPTER 9. INSTRUCTION SET9.4.10 Subroutine Stack Control InstructionsCALLF !faddrFunction: (SP-1) ← PC7 to PC4 , (SP-2) ← PC3 to PC0 ,(SP-3) ←

173CHAPTER 9. INSTRUCTION SETPUSH rpFunction: (SP-1) ← rpH, (SP-2) ← rpL, SP ← SP-2Saves the contents of register pair rp (XA, HL) to the data memo

174CHAPTER 9. INSTRUCTION SET9.4.11 Interrupt Control InstructionsEIFunction: IME ← 1Sets the interrupt master enable flag (1), and enables interru

175CHAPTER 9. INSTRUCTION SET9.4.12 Input/Output InstructionsIN A, PORTnFunction: A ← PORTn; n = N3 to N0 : 0 to 3, 5, 6Transfers the contents of t

176CHAPTER 9. INSTRUCTION SET9.4.13 CPU Control InstructionsHALTFunction: PCC. 2 ← 1Sets the HALT mode (This instruction sets bit 2 of the processo

177APPENDIX A. TABLE OF INSTRUCTION USABLE WITH EVAKIT-75X ONLYAPPENDIX A. TABLE OF INSTRUCTION USABLE WITH EVAKIT-75X ONLYSince EVAKI

178APPENDIX A. TABLE OF INSTRUCTION USABLE WITH EVAKIT-75X ONLYMnemonic OperandsDECS mem@HLSKE A, regXA, rp’XA, @HL@HL, #n4A, memSET1, CLR1, p

8CHAPTER 1. GENERALP30P31P32VSSP33P60P61NCNCNCNC123456789101112 13 14 15 16 17 18 19 20 21 22232425262728293

179APPENDIX B. DEVELOPMENT TOOLSAPPENDIX B. DEVELOPMENT TOOLSThe following development tools are available for system development using the µPD7

180APPENDIX B. DEVELOPMENT TOOLSDebugging ToolsThe following in-circuit emulators (IE-75000-R and IE-75001-R) are available as the µPD75402A progra

181APPENDIX B. DEVELOPMENT TOOLSDevelopment Tool Configuration*1.The IE-75001-R does not incorporatethe IE-75000-R-EM (Sold separately)2. EV-9200G-

182APPENDIX C. MASK ROM ORDERING PROCEDUREAPPENDIX C. MASK ROM ORDERING PROCEDUREWhen completing the µPD75402A program and ordering the mask

183APPENDIX D. INSTRUCTION INDEX (ALPHABETIC ORDER)APPENDIX D. INSTRUCTION INDEX (ALPHABETIC ORDER)ADDC A, @HLADDS A, #n4ADDS A, @HLAND A, @

184APPENDIX E. HARDWARE INDEX (ALPHABETIC ORDER)APPENDIX E. HARDWARE INDEX (ALPHABETIC ORDER)SymbolHardwareNamePageHardwareNamePageSymbolIRQ

The information in this document is subject to change without notice.No part of this document may be copied or reproduced in any form or by any means

9CHAPTER 1. GENERAL(2) PROM modeO0O1O2NCNCVSSNCO3O4O5NCA6A7A12VPPNCNCNCVDDA14A13NC1234567891011 2324252627282

CHAPTER 2. PIN FUNCTIONS10CHAPTER 2. PIN FUNCTIONSThe µPD75402A operates by the pin functions in the normal operating mode.For the µPD75P402’s p

11CHAPTER 2. PIN FUNCTIONSFunctionsA 4-bit input port (Port 0).For P01 to P03, it is designatable to build in the pull-up resistor bysoftware in 3-

CHAPTER 2. PIN FUNCTIONS12Dual-Function PinP10P12P03P02/SB0P01P02/SOP222.1.2 List of Pins Other Than Port PinsTable 2-2 List of Pins Other than Po

13CHAPTER 2. PIN FUNCTIONSPort 0 Dual-Function Pin Port 1 Dual-Function PinP00 P10 INT0P01 SCK P12 INT2P02 SO/SB0P03 SI2.2 NORMAL OPERATING MODE2.2

CHAPTER 2. PIN FUNCTIONS142.2.2 P20 to P23 (Port 2) ... PCL Dual-Function 3-Stae Input/OtputP30 to P33 (Port 3) ... 3-State Input/OutputP50 to

15CHAPTER 2. PIN FUNCTIONSV DDV DDX1X2PD75402AµCrystal Resonatoror Ceramic OscillatorX1X2PD74HC04µExternalClock(Standard 4.194304 MHz

CHAPTER 2. PIN FUNCTIONS162.3 PROM MODEThe PROM mode is designatable in the µPD75P402 alone.2.3.1 A0 to A14 (Address) ... InputA 15-bit address i

17CHAPTER 2. PIN FUNCTIONSInput/Output TypeµPD75402AµPD75P402P00 BP01/SCK F - AP02/SO/SB0 F - BP03/SI B - CP10/INT0 BP12/INT2 B - CP20, P21, P23P22

CHAPTER 2. PIN FUNCTIONS18VDDP-chP.U.R.enableINP.U.R.VDDP-chN-chOUTdataoutputdisableVDDP-chN-chINType A (for Types E - B)Type BTyp

Major Revisions in This VersionSection DescriptionAmendment: Fig. 5-52 “Data Transmission from Slave Deviceto Master Device”Change: Appendix B “Devel

19CHAPTER 2. PIN FUNCTIONSVDDIN/OUTN-ch (+10 VWithstandVoltage)dataoutputdisableP.U.R(Mask Option)IN/OUTN-ch (+10 VWithstandVoltage)d

CHAPTER 2. PIN FUNCTIONS20VDDVDDVDDVDDDiode withSmall VFP00, RESET P00, RESET2.5 UNUSED PIN TREATMENTPinP00P01 to P03P10 and P12P20 to P23P

CHAPTER 3. FEATURES OF ARCHITECTURE AND MEMORY MAP21CHAPTER 3. FEATURES OF ARCHITECTURE AND MEMORY MAPThe µPD75402A’s architecture is a

CHAPTER 3. FEATURES OF ARCHITECTURE AND MEMORY MAP22Adress000H003H020H03FHF80HFB0HFBFHFF0HFFFHTable 3-1 Data Memory Configuration and

CHAPTER 3. FEATURES OF ARCHITECTURE AND MEMORY MAP23Table 3-2 Addressing Mode ListAddressing Mode1-bit directaddressing4-bit directaddressing8-

CHAPTER 3. FEATURES OF ARCHITECTURE AND MEMORY MAP243.1.2 Data Memory Addressing ModesIn the µPD75402A, the 6 types of addressing modes listed

CHAPTER 3. FEATURES OF ARCHITECTURE AND MEMORY MAP25(3) 8-bit direct addressing (mem)An addressing mode to specify the whole data memory space

CHAPTER 3. FEATURES OF ARCHITECTURE AND MEMORY MAP26P30P61P53(i) SET1 CY ; CY ← 1AND1 CY, PORT3. 0 ; CY∧P30AND1 CY, PORT6. 1 ; CY∧P61SKT CY

CHAPTER 3. FEATURES OF ARCHITECTURE AND MEMORY MAP27(6) Stack addressingThis addressing mode is for the saving/restoring operation during the i

CHAPTER 3. FEATURES OF ARCHITECTURE AND MEMORY MAP283.2 MEMORY-MAPPED I/OThe µPD75402A adopts memory-mapped I/O to map such peripheral hardware

PREFACEUSERThis manual is intended for user engineers who wish to understand the µPD75402A’s, 75P402’s functions anddesign an application system using

CHAPTER 3. FEATURES OF ARCHITECTURE AND MEMORY MAP29WWBit 2 is fixed to 0.WWR/W R/WR/W R/WR/W R/WR/W R/WFB2HFB3HFB4HFB8HFBDHFBEHFBFHBit 0 is fi

CHAPTER 3. FEATURES OF ARCHITECTURE AND MEMORY MAP30* 1* 2* 3WWWRRRRR/W R/WR/W R/WR/W R/WR/W R/WPort 0 (PORT 0)Port 1 (PORT 1)Port 2 (PORT 2)Po

CHAPTER 4. INTERNAL CPU FUNCTIONS31The program counter operates as follows.• Normal operationThe content is incremented automatically according to

32CHAPTER 4. INTERNAL CPU FUNCTIONS4.2 PROGRAM MEMORY (ROM) ... 1,920 WORDS × 8 BITSA mask programmable ROM of a 1,920-word × 8-bit configuratio

CHAPTER 4. INTERNAL CPU FUNCTIONS334.3 DATA MEMORY (RAM)The data memory consists of the data and peripheral hardware areas as shown in Fig. 4-3.Fi

34CHAPTER 4. INTERNAL CPU FUNCTIONS(2) Peripheral hardware areaThe peripheral hardware area is mapped to memory bank 15’s addresses F80H to FFFH.T

CHAPTER 4. INTERNAL CPU FUNCTIONS354.4 GENERAL REGISTER ... 4 × 4 BITSThe general register is assigned to a specific address of the data memory.

36CHAPTER 4. INTERNAL CPU FUNCTIONS4.5 ACCUMULATORIn the µPD75402A, the A register and the XA register pair function as accumulators. The 4-bit da

CHAPTER 4. INTERNAL CPU FUNCTIONS374.6 STACK POINTER (SP) ... 8 BITSThe µPD75402A uses a static RAM as the stack memory (LIFO format). The 8-bit

38CHAPTER 4. INTERNAL CPU FUNCTIONSFig. 4-8 Data Saved to Stack MemoryStack Stack StackRegister PairLow OrderRegister PairHigh OrderSP - 2

Related DocumentationDevice Related DocumentsDocument Name Document NumberIE-75000-R/IE-75001-R User's Manual EEU-846IE-75000-R-EM User's Ma

CHAPTER 4. INTERNAL CPU FUNCTIONS394.7 PROGRAM STATUS WORD (PSW) ... 8 BITSThe program status word (PSW) consists of various flags concerning cl

40CHAPTER 4. INTERNAL CPU FUNCTIONSExample Take AND of bit 3 at address 3FH and P33 and set the result in CY.SET1 CY ; CY← 1SKT 3FH. 3 ; Skip if b

41CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONSCHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS5.1 DIGITAL INPUT/OUTPUT PORTSThe µPD75402A has the followin

42CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS5.1.1 Digital Input/Output Port Types, Characteristics and ConfigurationThe different types of digital i

43CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONSFig. 5-2 Configuration of Ports 0 and 1Input BufferInternal BusInput Buffer or fXX/64Noise Eliminat

44CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONSFig. 5-3 Configuration of Port 3Remarks n = 0 to 3Input BufferPM 3 n=0PM 3 n=1MPXOutput LatchPM

45CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONSFig. 5-4 Configuration of Ports 2 and 6* Input/output mode specification is performed by bit 2 (PM2) of

46CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONSFig. 5-5 Configuration of Port 5Pull-Up Resistors(Mask Option; µPD75402AOnly)5.1.2 Input/Output Mode Se

47CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONSFig. 5-6 Format of Port Mode RegistersPort Mode Register Group APort Mode Register Group BSpecification

48CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS(1) Bit handling instructionsDirect addressing of specific address bits (fmem.bit) can be used on all di

- i -CONTENTSCHAPTER 1. GENERAL...

49CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS5.1.4 Digital Input/Output Port OperationsPort and port pin operations when a data memory handling instr

50CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONSTable 5-3 Operations with Input/Output Port Handling InstructionsSKT PORTn.bitSKF PORTn.bitAND1 CY, POR

51CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS5.1.5 Internal Pull-up ResistorsThe µPD75402A can incorporate internal pull-up resistors for all port p

52CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONSFig. 5-7 Format of Pull-Up Resistor Specification RegisterAddress 7 6 5 43210 SymbolFDCH – PO6 – – PO3

53CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS5.1.6 Digital Input/Output Port Input/Output TimingThe timing for outputting data to the output latch an

54CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS5.2 CLOCK GENERATION CIRCUITThe clock generation circuit supplies various clocks to the CPU and peripher

55CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS5.2.2 Clock Generation Circuit Function and OperaionThe clock generation circuit generates the CPU clock

56CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONSFig. 5-11 Processor Clock Control Register FormatNote When using a calue of fXX such that 4.19 MHz <

57CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS(2) System clock oscillation circuitThe system clock oscillation circuit oscillates by means of a crysta

58CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONSFig. 5-13 Example of Poor Resonator Connection Circuit (2/2)(c) Signal line close to varyin high curren

- ii -CHAPTER 4. INTERNAL CPU FUNCTIONS ... 314.1 PROGRAM

59CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS; Assume PCC = 0011.MOV A, #00000.95 µs/4.19 MHz MOV PCC, A ; PCC ← 0000BR 16 machine cycles15.3 µs/4.19

60CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONSAs the PCC is set in 0 by RESET input, Φ is reset-started at the slowest speed (state in which the oper

61CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS5.2.4 Differences Between µPD75402A and µPD75402Part of the clock generation circuit differs between the

62CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONSNext, the processor clock control register (PCC) of the µPD75402 is shown below. Setting of bit 1 of the

63CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS5.3 CLOCK OUTPUT CIRCUITThe clock output circuit outputs clock pulses from the P22/PCL pin, and is used

64CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS5.3.2 Clock Output Mode Register (CLOM)CLOM is a 4-bit register used to control clock output.CLOM is set

65CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS5.3.3 Clock Output ProcedureClock pulse output is performed by the following procedure.(i) Set the clock

66CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS5.4 BASIC INTERVAL TIMERThe µPD75402A is equipped with an 8-bit basic interval timer which has the follo

67CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS5.4.2 Basic Intercal Timer Mode Register (BTM)BTM is a 4-bit register which controls the operation of th

68CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS5.4.3 Basic Interval Timer OperationThe basic interval timer (BT) is constantly incremented by the clock

- iii -6.5 MACHINE CYCLES BEFORE INTERRUPT SERVICING ... 1356.6 INTERRUPT A

69CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS5.4.4 Examples of Basic Interval Timer ApplicationsExample 1. In this example the basic interval timer

70CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS5.5 SERIAL INTERFACE5.5.1 Serial Interface FunctionsThe µPD75402A incorporates a clocked 8-bit serial in

71CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS(3) SBI mode (serial bus interface mode)In the SBI mode, communication is performed with multiple device

72CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONSFig. 5-24 Serial Interface Block DiagramInternal Bus8 88BitTestCSIMP03/SIP02/SO/SB0P01/SCKS

73CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS(1) Serial operating mode register (CSIM)CSIM is an 8-bit register which specifies the serial interface

74CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS(8) INTCSI control circuitControls the generation of interrupt requests. In the following case, the inte

75CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONSFig. 5-25 Serial Operating Mode Register (CSIM) Format (1/2)Address 7 6 5 4 3 2 1 0 SymbolFE0H CSIE COI

76CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONSNote If WUP = 1 is set during BUSY signal output, BUSY is not released. With the SBI, the BUSY signal is

77CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONSRemarks 1. The operating mode can be selected according to the setting of CSIE and CSIM3.CSIE CSIM3 Oper

78CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS(2) Serial bus interface control register (SBIC)The format of the serial bus interface control register

- iv -CONTENTS OF FIGURESFig. No Title Page3-1 Static RAM Address Updating Method ...

79CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONSFig. 5-26 Serial Bus Interface Control Register (SBIC) Format (2/3)Bus release trigger bit (W)RELTThe b

80CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONSFig. 5-26 Serial Bus Interface Control Register (SBIC) Format (3/3)Acknowledge enable bit (R/W)ACKEWhen

81CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS(3) Shift register (SIO)The configuration around the shift register is shown in Fig. 5-27. SIO is an 8-b

82CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS(4) Slave address register (SVA)SVA is an 8-bit register used by the slave to set the slave address valu

83CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS5.5.4 Operation-Halted ModeThe operation-halted mode is used when no serial transfer is performed, allow

84CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONSSerial clock selection bit (W)The P01/SCK pin status depends on the CSIM1 setting as shown below.CSIM1 P

85CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS(a) Serial operating mode register (CSIM)When the 3-wire serial I/O mode is used, CSIM is set as shown b

86CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONSSignal from address comparator (R)Clearing Conditions (COI = 0) Setting Condition (COI = 1)When slave ad

87CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS(b) Serial bus interface control register (SBIC)When the 3-wire serial I/O mode is used, SBIC is set as

88CHAPTER 5. PERIPHERAL HARDWARE FUNCTIONS(2) Communication operationIn the 3-wire serial I/O mode, data transmission/ reception is performed in 8