NEC PD78058FY(A) manuals

Nec PD78058FY(A) User Manual (593 pages)

Brand: Nec | Category: Hardware | Size: 3.09 MB |

English

Table of contents

PD78058F, 78058FY Subseries

1

NOTES FOR CMOS DEVICES

3

M7 96.5

4

Regional Information

5

bus interface) mode √ —

10

mode — √

10

Other Documents

13

LIST OF FIGURES (1/8)

23

LIST OF FIGURES (2/8)

24

LIST OF FIGURES (3/8)

25

LIST OF FIGURES (4/8)

26

LIST OF FIGURES (5/8)

27

LIST OF FIGURES (6/8)

28

LIST OF FIGURES (7/8)

29

LIST OF FIGURES (8/8)

30

LIST OF TABLES (1/3)

31

LIST OF TABLES (2/3)

32

LIST OF TABLES (3/3)

33

CHAPTER 1 OUTLINE (

35

1.1 Features

35

1.2 Applications

36

1.3 Ordering Information

36

1.4 Quality Grade

37

CHAPTER 1 OUTLINE (

38

12 mm)

38

Pin Identifications

39

1.6 78K/0 Series Expansion

41

10-bit timer: 1 channel

42

2. 10-bit timer: 1 channel

42

1.7 Block Diagram

43

1.8 Outline of Function

44

1.9 Differences Between the

45

PD78058F and

45

PD78058F(A)

45

1.10 Mask Options

46

CHAPTER 2 OUTLINE (

47

2.1 Features

47

2.2 Applications

48

2.3 Ordering Information

48

2.4 Quality Grade

49

CHAPTER 2 OUTLINE (

50

2.6 78K/0 Series Expansion

53

2.7 Block Diagram

55

2.8 Outline of Function

56

2.9 Differences Between the

57

PD78058FY and

57

PD78058FY(A)

57

2.10 Mask Options

58

CHAPTER 3 PIN FUNCTION (

59

3.1 Pin Function List

59

(1) Port pins (2/3)

60

(2) Non-port pins (1/2)

62

DD — Positive power supply

64

SS — Ground potential

64

CHAPTER 3 PIN FUNCTION (

65

As short as possible

72

CHAPTER 4 PIN FUNCTION (

77

4.1 Pin Function List

77

CHAPTER 4 PIN FUNCTION (

83

CHAPTER 5 CPU ARCHITECTURE

95

5.1 Memory Spaces

95

Figure 5-2. Memory Map (

96

PD78058F, 78058FY)

101

PD78P058F, 78P058FY)

102

5.2 Processor Registers

103

CHAPTER 5 CPU ARCHITECTURE

104

Register Register

106

(b) Function Name

107

(a) Absolute Name

107

Identifier Description

117

01010000 50H (immediate data)

120

[Illustration]

121

— [DE], [HL]

122

— [HL + byte]

123

— [HL + B], [HL + C]

124

CHAPTER 6 PORT FUNCTIONS

125

6.1 Port Functions

125

Table 6-1. Port Functions (

126

PD78058F Subseries) (1/2)

126

Table 6-2. Port Functions (

128

PD78058FY Subseries) (1/2)

128

6.2 Port Configuration

130

CHAPTER 6 PORT FUNCTIONS

131

P00/INTP0/TI00

131

Internal bus

131

PM : Port mode register

136

RD : Port 2 read signal

136

WR : Port 2 write signal

136

RD : Port 7 read signal

143

WR : Port 7 write signal

143

P10 to P17

147

Input/Output

147

ANO0, ANO1 Output 1 ×

147

6.4 Port Function Operations

152

6.5 Selection of Mask Option

153

CHAPTER 7 CLOCK GENERATOR

155

Selector

156

Feedback resistor

157

CHAPTER 7 CLOCK GENERATOR

158

X = 5.0 MHz, fXT = 32.768 kHz

159

Remarks f

160

7.4 System Clock Oscillator

161

X2 ICX1 X2 ICX1

162

(n = 0 to 7, 12, 13)

162

X = 5.0 MHz and f

168

XT = 32.768 kHz

168

X) is secured automatically

169

8.1 Overview of the

171

Watch Timer Watchdog Timer

172

X = 5.0 MHz

173

Inversion operation disabled

183

Inversion operation enabled

183

CRC00CRC01CRC02

190

CRC0 00/10/100000

190

CR00 set as compare register

190

AN = VREF ×

191

≤ CR01 < CR00 ≤ FFFFH

192

CRC0 00/1100000

193

CR01 set as capture register

193

CRC0 10100000

195

CR00 set as capture register

195

OVF0TMC01TMC02TMC03

200

TMC0 00/1110000

202

TMC0 00110000

204

Timer Start

208

Count Pulse

208

2, respectively

217

SCK : Serial clock frequency

218

TM1, TM2 Count Value

236

00H 01H 02H 03H 04H

236

CR10, CR20

237

X-1 X FFH 00H 01H 02H

237

CHAPTER 10 WATCH TIMER

239

10.1 Watch Timer Functions

239

CHAPTER 10 WATCH TIMER

240

10.4 Watch Timer Operations

244

CHAPTER 11 WATCHDOG TIMER

245

CHAPTER 11 WATCHDOG TIMER

246

PCL/P35 Pin Output

253

CHAPTER 14 A/D CONVERTER

261

14.1 A/D Converter Functions

261

CHAPTER 14 A/D CONVERTER

262

14.5 A/D Converter Cautions

274

CHAPTER 15 D/A CONVERTER

279

15.1 D/A Converter Functions

279

CHAPTER 15 D/A CONVERTER

280

PD78058F, 78058FY

284

PD78058F SUBSERIES)

285

RESET input sets SBIC to 00H

302

SO0 latch

303

"H"

308

SB0 (SB1)

308

D7 D6 D5 D4 D3 D2 D1 D0

310

12345678

310

(4) Various signals

317

Figure 16-22. ACKT Operation

318

Figure 16-25. BSYE Operation

320

ACK BUSY

321

Note 2 Note 2

332

SO0 Latch

335

PD78058FY SUBSERIES)

337

Note 2

350

SDA0(SDA1)

365

(b) Data

375

(c) Stop Condition

376

Wait request signal

386

Timer Clock

389

Select Register 3

389

BUSY1 BUSY0

394

Shift Register 1

400

Operation

400

Interval Interval

419

D7 D6 D5

419

Interval

429

TPS3 TPS2 TPS1 TPS0

436

MDL3 MDL2 MDL1 MDL0

436

RESET input sets ASIM to 00H

447

RESET input sets BRGC to 00H

463

SCK) selected with

469

CY = 0.4

469

CY = 0.2

469

[Example]

470

PSW and PC Save, Jump

492

CPU: CPU clock)

496

1 Instruction

499

Execution

499

21.5 Test Functions

502

(a) Memory Map of the

506

Lower Address

513

CHAPTER 23 STANDBY FUNCTION

515

X, not 2

516

Oscillation

519

XT is selected as

520

X: 5.0 MHz

522

CHAPTER 24 RESET FUNCTION

523

24.1 Reset Function

523

CHAPTER 24 RESET FUNCTION

525

CHAPTER 25 ROM CORRECTION

527

25.1 ROM Correction Functions

527

Source program

530

25.5 ROM Correction Example

533

25.6 Program Execution Flow

534

CHAPTER 26

537

PD78P058F, 78P058FY

537

26.3 PROM Programming

540

G = Start address

542

N = Last address of program

542

G = Start address

544

A0 to A16

545

D0 to D7

545

DD and VPP pins

546

CHAPTER 27 INSTRUCTION SET

549

CHAPTER 27 INSTRUCTION SET

550

27.2 Operation List

552

Note 1 Note 2

554

8 + n + m

556

12 + n + m

556

(1) 8-bit instructions

560

[HL + B] $addr16

561

[HL + C]

561

78058FY Subseries

567

Hardware

569

B.2 PROM Programming Tool

571

B.3 Debugging Tool

572

B.4 OS for IBM PC

576

Based on EV-9200GC-80

577

(1) Package drawing (in mm)

577

Reference diagram: TGK-080SDW

579

Package dimension (unit: mm)

579

C.1 Real-time OS (1/2)

582

Real-time OS (2/2)

583

APPENDIX D REGISTER INDEX

585

APPENDIX D REGISTER INDEX

586

APPENDIX E REVISION HISTORY

591

Facsimile

593

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