Nec PD78214 User Manual

USER'S MANUALµPD78214 SUB-SERIES8-BIT SINGLE-CHIP MICROCOMPUTERHARDWAREµPD78212µPD78213µPD78214µPD78P214µPD78212 (A)µPD78213 (A)µPD78214 (A)µPD78

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71Chapter 5 Port Functions5Fig. 5-13 Block Diagram of P33 (Port 3)★5.4.2 Setting the I/O Mode and Control ModeThe port 3 mode register (PM3) can p

72µPD78214 Sub-SeriesFig. 5-14 Port 3 Mode Register FormatFig. 5-15 Port 3 Mode Control Register (PMC3) FormatPM377PM366PM355PM344PM333PM322PM311PM3

73Chapter 5 Port Functions55.4.3 OperationPort 3 is an I/O port. Its pins also function as control signal pins.(1) Output portWhen port 3 is in th

74µPD78214 Sub-Series(3) Control signal input or outputRegardless of setting of the port mode 3 register (PM3), each bit of port 3 can be used to inpu

75Chapter 5 Port Functions5Fig. 5-20 Connection of Pull-Up Resistors (Port 3)5.5 PORT 4Port 4 is an 8-bit I/O port with an output latch. The memo

76µPD78214 Sub-Series5.5.1 Hardware ConfigurationFig. 5-21 shows the hardware configuration of port 4.Fig. 5-21 Block Diagram of Port 45.5.2 Settin

77Chapter 5 Port Functions55.5.3 OperationPort 4 is an I/O port. It functions also as an address/data bus (AD0 through AD7).(1) Output portWhen po

78µPD78214 Sub-Series(3) Address/data bus (AD0 through AD7)Port 4 is used as the address/data automatically for external access.Do not execute I/O ins

79Chapter 5 Port Functions5Fig. 5-25 Connection of Pull-Up Resistors (Port 4)5.5.5 Driving LEDs DirectlyFor port 4, the low level side of the outp

80µPD78214 Sub-Series5.6 PORT 5Port 5 is an 8-bit I/O port with an output latch. The port 5 mode register (PM5) can put each bit of this port in eit

81Chapter 5 Port Functions5Fig. 5-28 Port 5 Mode Register FormatTable 5-6 Port 5 Operating Modes11001×MM201×MM1×1×MM0EA pinMM register bitOperatio

82µPD78214 Sub-SeriesFig. 5-30 Port Specified as an Input PortCaution Although its ultimate purpose is to manipulate only 1 bit, a bit manipulation i

83Chapter 5 Port Functions5Fig. 5-32 Connection of Pull-Up Resistors (Port 5)5.6.5 Driving LEDs DirectlyFor port 5, the low level side of the outp

84µPD78214 Sub-Series5.7 PORT 6Port 6 is an 8-bit I/O port with an output latch. P64 through P67 have a software-programmable built-in pull-upresist

85Chapter 5 Port Functions5(vi) AN6 and AN7 (analog input)These pins receive analog signals for the A/D converter.5.7.1 Hardware ConfigurationFig.

86µPD78214 Sub-SeriesFig. 5-35 Block Diagram of P64 and P65 (Port 6)Internal busP64(P65)VDDRDINSelectorRDPUOWRPUOPull-up resistor option registerPUO6

87Chapter 5 Port Functions5Fig. 5-36 Block Diagram of P66 (Port 6)Internal busP66VDDRDINRDPUOWRPUOPull-up resistor option registerPUO6Port 6 mode r

88µPD78214 Sub-SeriesFig. 5-37 Block Diagram of P67 (Port 6)5.7.2 Setting the I/O Mode and Control ModeThe port 6 mode register (PM6) can put port 6

89Chapter 5 Port Functions5Cautions 1. To use P60 through P63 as an output port, it is necessary to reset the PM60 through PM63 bits to 0. If they

90µPD78214 Sub-Series5.7.3 OperationPort 6 is an I/O port. Its pins also function as control signal pins.(1) Output portWhen port 6 is in the output

- i -ContentsCONTENTSCHAPTER 1 GENERAL ...

91Chapter 5 Port Functions5(3) Control pinsWhen port 6 function as control pins, they cannot be manipulated or tested by software.(4) Analog inputs

92µPD78214 Sub-Series5.7.5 NoteWhen P66 and P67 are used as analog input pins AN6 and AN7 respectively or when A/D conversion is notperformed, do not

93Chapter 5 Port Functions55.8.3 OperationPort 7 is an input-only port, and the level of its pins can be read and tested.Fig. 5-44 Port Specified

94µPD78214 Sub-Series(4) P22 through P26 are not pulled up immediately after a reset, and the interrupt request flag may be setdepending on the functi

956CHAPTER 6 REAL-TIME OUTPUT FUNCTION6.1 CONFIGURATION AND FUNCTIONThe real-time output function is implemented by the hardware centering around po

96µPD78214 Sub-SeriesFig. 6-1 Block Diagram of the Real-Time Output Port444P00P01P02P03P04P05P06P07INTP0P0MLINTC10SelectorSelectorP0MHP0MLEXTRP0MHBYT

97Chapter 6 Real-Time Output Function66.2 REAL-TIME OUTPUT CONTROL REGISTER (RTPC)The real-time output control register (RTPC) is an 8-bit register

98µPD78214 Sub-SeriesTable 6-1 Port 0 Operating Modes and Operations Needed for the Port 0 Buffer Registers8-bit port mode8-bit real-timeoutput portm

99Chapter 6 Real-Time Output Function66.4 OPERATIONWhen port 0 is in the real-time output port mode, the contents of the buffer registers (P0H and

100µPD78214 Sub-SeriesFig. 6-4 Real-Time Output Port Operation TimingD02D03D02D01D00 D01D03D040HCR11CR11CR11CR11FFHTimer startsINTC11 interruptreques

- ii -Contents3.3 NOTES ...

101Chapter 6 Real-Time Output Function6Fig. 6-5 Real-Time Output Port Operation Timing (Controlling 2 Channels Independently of Each Other)8-bit ti

102µPD78214 Sub-Series6.5 APPLICATION EXAMPLEThis section describes an example of application in which P00 through P03 are used as a 4-bit real-time

103Chapter 6 Real-Time Output Function6Fig. 6-7 Contents of the Control Register for the Real-Time Output Function7654321000000001RTPCUses pins P00

104µPD78214 Sub-SeriesFig. 6-9 Interrupt Request Handling When the Real-Time Output Function Is Used6.6 NOTES(1) When the P0ML or P0MH is set to 1,

105Chapter 6 Real-Time Output Function6(4) With an in-circuit emulator, digital noise cannot be eliminated normally from the INTP0 pin. When it iss

106

1077CHAPTER 7 TIMER/COUNTER UNITSThe µPD78214 contains one 16-bit timer/counter unit (channel) and three 8-bit timer/counter units (channels).Table 7

108µPD78214 Sub-SeriesFig. 7-1 Block Diagrams of Timer/Counter Units16-bit timer/counter unitfCLK/8Timer register TM0Compare register CR00OVFCompare

109Chapter 7 Timer/Counter Units77.1 16-BIT TIMER/COUNTER7.1.1 FunctionsThe 16-bit timer/counter can function as an interval timer and can also be

110µPD78214 Sub-SeriesFig. 7-2 Block Diagram of 16-Bit Timer/Counter8CLR01Compare register (CR01)8ENTO116ALV0ENTO0ALV1Internal busTimer outputcontrol

- iii -ContentsPreface5.8.4 Built-In Pull-Up Resistor ...935.

111Chapter 7 Timer/Counter Units7(1) 16-bit timer 0 (TM0)TM0 is a count-up timer using a count clock of fCLK/8.The count operation of TM0 can be ena

112µPD78214 Sub-SeriesFig. 7-3 Format of Timer Control Register 0 (TMC0)76543210CE3 0 0 0 CE0 OVF0 0 0TMC0OVF00110CE0TM0 overflow flagOverflow does n

113Chapter 7 Timer/Counter Units7(3) Timer output control register (TOC)The TOC register is an 8-bit register for specifying the active level of tim

114µPD78214 Sub-Series7.1.4 Operation of 16-Bit Timer 0 (TM0)(1) Basic operationThe 16-bit timer/counter performs count operation by counting up with

115Chapter 7 Timer/Counter Units7(c) When the value of TM0 is FFFFHCount clock fCLK/8TM0Cleared by softwareOVF0FFFEHFFFFH0H 1HOVF0←0(2) Cl

116µPD78214 Sub-SeriesFig. 7-8 Clear Operation When the CE0 Bit Is Reset to 0(a) Basic operationTM0CE0n-1 n0Count clock(b) Restart after 0 is set i

117Chapter 7 Timer/Counter Units77.1.5 Compare Register and Capture Register Operations(1) Compare operationThe 16-bit timer/counter performs an op

118µPD78214 Sub-SeriesFig. 7-10 TM0 Cleared After a Coincidence Is DetectedRemark CLR01 = 1(2) Capture operationThe 16-bit timer/counter performs a

119Chapter 7 Timer/Counter Units7Fig. 7-11 Capture OperationRemark Dn: TM0 count value (n = 0, 1, 2, ...)CLR01 = 0Caution With an in-circuit emula

120µPD78214 Sub-SeriesTable 7-5 Timer Output (TO0, TO1) OperationTOC0011011011011ENTO10/10/10/10/10/10/10/10/10/10/10/10/10/1ALV10101101101101ENTO00/

- iv -Contents7.4.6 Sample Applications ...2117.5 NOT

121Chapter 7 Timer/Counter Units7(1) Basic operationBy setting ENTOn (n = 0, 1) of the timer output control register (TOC) to 1, the timer outputs (

122µPD78214 Sub-Series7.1.7 PWM OutputThe PWM output function outputs a PWM signal whose period coincides with the full-count period of 16-bit timer0

123Chapter 7 Timer/Counter Units7Fig. 7-14 Example of PWM Output Using TM0Remark ALV0 = 0, ALV1 = 0Fig. 7-15 PWM Output When CR00 = FFFFHRemark

124µPD78214 Sub-SeriesEven if the value of a compare register (CR00, CR01) coincides with the value of 16-bit timer 0 (TM0) more thanonce during one p

125Chapter 7 Timer/Counter Units72. If timer output is disabled (ENTOn = 0: n = 0, 1), the output level on the TOn (n = 0, 1) pin is the inverted va

126µPD78214 Sub-SeriesFig. 7-19 PPG Output When CR00 = CR01Fig. 7-20 PPG Output When CR00 = 0000HRemark ALV0 = 012nnnINTC00INTC01TO0TM0count valuen

127Chapter 7 Timer/Counter Units7Even if the value of the CR00 compare register coincides with the value of 16-bit timer 0 (TM0) more than oncedurin

128µPD78214 Sub-Series2. If the current value of the CR01 compare register is decreased below the value of 16-bit timer 0 (TM0), the PPG period become

129Chapter 7 Timer/Counter Units77.1.9 Sample Applications(1) Interval timer operation (1)By free running 16-bit timer 0 (TM0), and adding a value

130µPD78214 Sub-SeriesFig. 7-25 Setting of Control Registers for Interval Timer Operation (1)(a) Timer control register 0 (TMC0)(b) Capture/compare

- v -Contents10.4 OPERATIONS IN THE THREE-WIRE SERIAL I/O MODE ...26510.4.1 Basic Operation Timing ..

131Chapter 7 Timer/Counter Units7Fig. 7-27 Interrupt Request Handling for Interval Timer Operation (1)(2) Interval timer operation (2)The 16-bit ti

132µPD78214 Sub-SeriesFig. 7-29 Setting of Control Registers for Interval Timer Operation (2)(a) Timer control register 0 (TMC0)76543210000010 01CRC

133Chapter 7 Timer/Counter Units7Fig. 7-31 Timing of Pulse Width MeasurementRemark Dn: TM0 count value (n = 0, 1, 2, ...)Fig. 7-32 Setting of Co

134µPD78214 Sub-Series(c) External interrupt mode register 1 (INTM1)Fig. 7-33 Setting Procedure for Pulse Width MeasurementFig. 7-34 Interrupt Requ

135Chapter 7 Timer/Counter Units7(4) PWM output operationIn PWM output operation, a pulse signal with a duty factor determined by the value set in a

136µPD78214 Sub-SeriesFig. 7-37 Setting Procedure for PWM OutputFig. 7-38 Changing Duty Factor of PWM OutputCIF00←0Preprocessing for changing duty f

137Chapter 7 Timer/Counter Units7(5) PPG output operationIn PPG output operation, a pulse signal with a period and duty factor determined by the val

138µPD78214 Sub-SeriesFig. 7-41 Setting Procedure for PPG OutputPPG outputSet CRC0 registerSet TOC registerSet P34 pin in control modeSet period in

139Chapter 7 Timer/Counter Units77.2 8-BIT TIMER/COUNTER 17.2.1 FunctionsEight-bit timer/counter 1 can function as an interval timer and can also

140µPD78214 Sub-Series7.2.2 ConfigurationEight-bit timer/counter 1 consists of one 8-bit timer 1 (TM1), one 8-bit compare register (CR10), and one 8-

- vi -Contents12.3.4 Multiplexed-Interrupt Handling...31312.3.5 Interrupt

141Chapter 7 Timer/Counter Units7Fig. 7-43 Block Diagram of 8-Bit Timer/Counter 1Internal bus88PRS12ES01Timer control register 0 (TMC1)ClearPRS11 P

142µPD78214 Sub-Series(1) 8-bit timer 1 (TM1)TM1 is a timer for counting up with the count clock specified by the lower 4 bits of prescaler mode regis

143Chapter 7 Timer/Counter Units77.2.3 8-Bit Timer/Counter 1 Control Registers(1) Timer control register 1 (TMC1)The TMC1 register is an 8-bit regi

144µPD78214 Sub-SeriesFig. 7-45 Format of Prescaler Mode Register 1 (PRM1)76543210PRM1 PRS230PRS120 0 00 0 10

145Chapter 7 Timer/Counter Units77.2.4 Operation of 8-Bit Timer 1 (TM1)(1) Basic operationEight-bit timer/counter 1 performs count operation by cou

146µPD78214 Sub-Series(c) When the value of TM1 is FFHCount clockTM1Cleared by softwareOVF1OVF1←0FEH FFH 0H 1H(2) Clear operationAfter a coincidence

147Chapter 7 Timer/Counter Units7Fig. 7-49 TM1 Cleared after Capture OperationTM1Count clockn-1n012INTP0TM1 is captured to CR11 hereCleared hereTM1

148µPD78214 Sub-Series(b) Restart after 0 is set in TM1 clearedCount clockTM1CE1n-1n001When the CE1 bit is set to 1 aftr this count clock,counting st

149Chapter 7 Timer/Counter Units7Fig. 7-51 Compare OperationRemark CLR10 = 0, CLR11 = 0, CM = 0Caution When using an in-circuit emulator, see t

150µPD78214 Sub-SeriesFig. 7-53 Capture OperationRemark Dn: TM1 count value (n = 0, 1, 2, ...)CLR10 = 0, CLR11 = 0, CM = 1Count startsTM1 count va

- vii -ContentsCHAPTER 16 APPLICATION EXAMPLES ...

151Chapter 7 Timer/Counter Units7Fig. 7-54 TM1 Cleared after Capture OperationsRemark Dn: TM1 count value (n = 0, 1, 2, ...)CLR10 = 0, CLR11 = 0,

152µPD78214 Sub-SeriesFig. 7-55 Timing of Interval Timer Operation (1)nn0HTM1count valueMOD(2n)MOD(3n)FFHMOD(2n)MOD(3n)MOD(4n)Timer startsCompare reg

153Chapter 7 Timer/Counter Units7Fig. 7-57 Setting Procedure for Interval Timer Operation (1)Fig. 7-58 Interrupt Request Handling for Interval Tim

154µPD78214 Sub-SeriesFig. 7-59 Timing of Interval Timer Operation (2) (When CR11 Is Used As a Compare Register)Remark Interval = (n + 1) × x/fCLK,

155Chapter 7 Timer/Counter Units7Fig. 7-61 Setting Procedure for Interval Timer Operation (2)(3) Pulse width measurement operationIn pulse width me

156µPD78214 Sub-SeriesFig. 7-62 Timing of Pulse Width Measurement (When CR11 Is Used As a Capture Register)Remark Dn: TM1 count value (n = 0, 1, 2,

157Chapter 7 Timer/Counter Units7Fig. 7-63 Setting of Control Registers for Pulse Width Measurement(a) Timer control register 1 (TMC1)(b) Prescal

158µPD78214 Sub-SeriesFig. 7-64 Setting Procedure for Pulse Width MeasurementFig. 7-65 Interrupt Request Handling for Pulse Width CalculationSet CRC

159Chapter 7 Timer/Counter Units77.3 8-BIT TIMER/COUNTER 27.3.1 FunctionsEight-bit timer/counter 2 has two functions not available with the other

160µPD78214 Sub-Series(2) Programmable square wave outputEight-bit timer/counter 2 outputs a square wave separately on the TO2 and TO3 timer output pi

- viii -ContentsLIST OF FIGURESFig. No. Title, Page2-1 I/O Circuits Provided for Pins...

161Chapter 7 Timer/Counter Units7(4) External event counterEight-bit timer/counter 2 counts clock pulses (CI pin input pulses) applied to the extern

162µPD78214 Sub-SeriesFig. 7-66 Block Diagram of 8-Bit Timer/Counter 2External interruptmode registerINTC21RESET88888881/8ES21 ES20 ES11 ES10(INTM0)I

163Chapter 7 Timer/Counter Units7(5) Output control circuitWhen the value of CR20 or CR21 coincides with the value of TM2, timer output can be inver

164µPD78214 Sub-Series(2) Prescaler mode register 1 (PRM1)The PRM1 register is an 8-bit register used to specify a count clock for 8-bit timer 1 (TM1)

165Chapter 7 Timer/Counter Units7(3) Capture/compare control register 2 (CRC2)The CRC2 register is used to specify the condition for enabling the cl

166µPD78214 Sub-Series(4) Timer output control register (TOC)The TOC register is an 8-bit register for controlling the active level of timer output an

167Chapter 7 Timer/Counter Units77.3.4 Operation of 8-Bit Timer 2 (TM2)(1) Basic operationEight-bit timer/counter 2 performs count operation by cou

168µPD78214 Sub-Series(c) When the value of TM2 is FFH(2) Clear operationAfter a coincidence with the CR21 compare register or capture operation, 8-b

169Chapter 7 Timer/Counter Units7TM2 can also be cleared by software when the CE2 bit of the timer control register (TMC1) is reset to 0.Similarly,

170µPD78214 Sub-Series(c) Restart before 0 is set in TM2 clearedCount clockTM2CE2n-1When the CE2 bit is set to 1 before this count clock, ClearingTM2

12345678GENERALPIN FUNCTIONSCPU FUNCTIONCLOCK GENERATORPORT FUNCTIONSREAL-TIME OUTPUT FUNCTIONTIMER/COUNTER UNITSA/D CONVERTER9ASYNCHRONOUS SERIAL INT

- ix -ContentsFig. No. Title, Page5-25 Connection of Pull-Up Resistors (Port 4) ...

171Chapter 7 Timer/Counter Units7Fig. 7-75 External Event Count Timing of 8-Bit Timer/Counter 2(1) When occurrences of one edge are counted (maximu

172µPD78214 Sub-SeriesThe count operation of TM2 is controlled by the CE2 bit of the TMC1 register as in the case of basic operation.When the CE2 bit

173Chapter 7 Timer/Counter Units7Fig. 7-77 Example Where Input of No Valid Edge Cannot Be Distinguished from Input of Only One Valid Edgewith Extern

174µPD78214 Sub-Series(b) Count value read processing3. With an in-circuit emulator, digital noise on the CI/INTP2 pin cannot be removed correctly.

175Chapter 7 Timer/Counter Units77.3.6 One-Shot Timer FunctionEight-bit timer/counter 2 has an operation mode in which the full-count (FFH) is reac

176µPD78214 Sub-Series7.3.7 Compare Register and Capture Register Operations(1) Compare operationEight-bit timer/counter 2 performs an operation to c

177Chapter 7 Timer/Counter Units7Fig. 7-81 TM2 Cleared After a Coincidence Is DetectedRemark CLR22 = 0Caution When using an in-circuit emulator,

178µPD78214 Sub-SeriesFig. 7-82 Capture OperationRemark Dn: TM2 count value (n = 0, 1, 2, ...)CLR21 = 0, CLR22 = 0D0D1D2D0D1D2(undefined)(undefined

179Chapter 7 Timer/Counter Units7Fig. 7-83 TM2 Cleared after Capture OperationRemark CLR21 = 0, CLR22 = 17.3.8 Basic Operation of Output Control

180µPD78214 Sub-SeriesTable 7-15 Timer Output (TO2, TO3) OperationTOC0011011011011ENTO30/10/10/10/10/10/10/10/10/10/10/10/10/1ALV30101101101101ENTO20

- x -ContentsFig. No. Title, Page7-16 Example of Rewriting Compare Register CR00 ...

181Chapter 7 Timer/Counter Units7(1) Basic operationBy setting ENTOn (n = 2, 3) of the timer output control register (TOC) to 1, the timer outputs (

182µPD78214 Sub-SeriesTable 7-16 TO2 and TO3 Toggle Output (fCLK = 6 MHz)Count clockfCLK/16fCLK/32fCLK/64fCLK/128fCLK/256fCLK/512Maximum pulse width2

183Chapter 7 Timer/Counter Units7Table 7-17 PWM Output on TO2 and TO3 (fCLK = 6 MHz)Count clockfCLK/16fCLK/32fCLK/64fCLK/128fCLK/256fCLK/512Minimum

184µPD78214 Sub-SeriesFig. 7-87 PWM Output When CR20 = FFHRemark ALV2 = 0Even if the value of a compare register (CR20, CR21) coincides with the val

185Chapter 7 Timer/Counter Units7Cautions 1. If a value less than the value of 8-bit timer 2 (TM2) is set in a compare register (CR20, CR21), a PWM

186µPD78214 Sub-SeriesFig. 7-90 shows an example of PPG output using 8-bit timer 2 (TM2). Fig. 7-91 shows an example of PPG outputwhen CR20 = CR21.

187Chapter 7 Timer/Counter Units7Fig. 7-91 PPG Output When CR20 = CR21Remark ALV2 = 0Fig. 7-92 PPG Output When CR20 = 00HRemark ALV2 = 012nnnINT

188µPD78214 Sub-SeriesEven if the value of the CR20 compare register coincides with the value of 8-bit timer 2 (TM2) more than once duringone period o

189Chapter 7 Timer/Counter Units72. If the current value of the CR21 compare register is decreased below the value of 8-bit timer 2 (TM2), the PPG p

190µPD78214 Sub-Series7.3.11 Sample Applications(1) Interval timer operation (1)By free running 8-bit timer 2 (TM2), and adding a value to a compare

- xi -Contents7-62 Timing of Pulse Width Measurement ...1567-6

191Chapter 7 Timer/Counter Units7Fig. 7-97 Setting of Control Registers for Interval Timer Operation (1)(a) Prescaler mode register 1 (PRM1)(b) C

192µPD78214 Sub-SeriesFig. 7-99 Interrupt Request Handling for Interval Timer Operation (1)(2) Interval timer operation (2)Eight-bit timer/counter 2

193Chapter 7 Timer/Counter Units7Fig. 7-101 Setting of Control Registers for Interval Timer Operation (2)(a) Prescaler mode register 1 (PRM1)(b)

194µPD78214 Sub-SeriesFig. 7-102 Setting Procedure for Interval Timer Operation (2)(3) Pulse width measurement operationIn pulse width measurement, t

195Chapter 7 Timer/Counter Units7Fig. 7-103 Timing of Pulse Width MeasurementRemark Dn: TM2 count value (n = 0, 1, 2, ...)Fig. 7-104 Setting of

196µPD78214 Sub-Series(c) Timer control register 1 (TMC1)(d) External interrupt mode register 0 (INTM0)Fig. 7-105 Setting Procedure for Pulse Width

197Chapter 7 Timer/Counter Units7Fig. 7-106 Interrupt Request Handling for Pulse Width Calculation(4) PWM output operationIn PWM output operation,

198µPD78214 Sub-SeriesFig. 7-108 Setting of Control Registers for PWM Output Operation(a) Timer control register 1 (TMC1)(b) Prescaler mode registe

199Chapter 7 Timer/Counter Units7Fig. 7-109 Setting Procedure for PWM Output Fig. 7-110 Changing Duty Factor of PWM Output(5) PPG output operation

200µPD78214 Sub-SeriesFig. 7-112 Setting of Control Registers for PPG Output Operation(a) Timer control register 1 (TMC1)(b) Prescaler mode registe

- xii -Contents7-106 Interrupt Request Handling for Pulse Width Calculation ...1977-107 Exampl

201Chapter 7 Timer/Counter Units7Fig. 7-113 Setting Procedure for PPG Output Fig. 7-114 Changing Duty Factor of PPG Output(6) External event count

202µPD78214 Sub-SeriesFig. 7-116 Setting of Control Registers for External Event Counter Operation(a) Prescaler mode register 1 (PRM1)(b) External

203Chapter 7 Timer/Counter Units7(7) One-shot timer operationWhen functioning as a one-shot timer, 8-bit timer/counter 2 generates only one interrup

204µPD78214 Sub-SeriesFig. 7-120 Setting Procedure for One-Shot Timer OperationFig. 7-121 Procedure for Starting an Additional One-Shot Timer Operat

205Chapter 7 Timer/Counter Units77.4 8-BIT TIMER/COUNTER 37.4.1 FunctionsEight-bit timer/counter 3 can be used as an interval timer, and also as a

206µPD78214 Sub-SeriesFig. 7-122 Block Diagram of 8-Bit Timer/Counter 3INTP4/ASCKES41,ES40881/8ES41 ES40INTP4INTC30fCLK/512fCLK/256fCLK/128fCLK/64fCL

207Chapter 7 Timer/Counter Units77.4.3 8-Bit Timer/Counter 3 Control Registers(1) Timer control register 0 (TMC0)The TMC0 register is an 8-bit regi

208µPD78214 Sub-Series7.4.4 Operation of 8-Bit Timer 3 (TM3)(1) Basic operationEight-bit timer/counter 3 performs count operation by counting up with

209Chapter 7 Timer/Counter Units7(2) Clear operationAfter a coincidence with the CR30 compare register, 8-bit timer 3 (TM3) can be automatically cle

210µPD78214 Sub-Series(b) Restart after 0 is set in TM3 clearedCount clockTM3CE3n-1n001When the CE3 bit is set to 1 after this count clock,counting s

- xiii -Contents8-9 Software-Started Scan-Mode A/D Conversion ...2358-10 Exam

211Chapter 7 Timer/Counter Units7Fig. 7-128 Compare Operation7.4.6 Sample Applications(1) Interval timer operationEight-bit timer/counter 3 can be

212µPD78214 Sub-SeriesFig. 7-130 Setting of Control Registers for Interval Timer Operation(a) Timer control register 0 (TMC0)(b) Prescaler mode reg

213Chapter 7 Timer/Counter Units7(2) The OVFm flag for holding an overflow from a timer/counter is contained in register TMCn used to control theope

214µPD78214 Sub-SeriesFig. 7-132 Count Start Operation(5) Even when an instruction is executed to stop a timer (CEn ← 0), the value of TMn is not cle

215Chapter 7 Timer/Counter Units7(6) When a register associated with a timer/counter is accessed, wait states as many as the maximum numberof clock

216µPD78214 Sub-Series(9) When PWM is used, a PWM signal with a 100% duty factor is output if a value less than the value of TMn (n= 0, 2) is set in c

217Chapter 7 Timer/Counter Units7(10)Notes on compare register rewrite operation when PPG output is used(a) If a value less than the value of TMn is

218µPD78214 Sub-SeriesFig. 7-137 Example of PPG Output Period Made Longern3n1n2n4n20HCRn0CRn1TOp(p = 0,2)n1n3n1n4n2n1Full count valuen3n5TMnThe PPG p

219Chapter 7 Timer/Counter Units7(14) With an in-circuit emulator, digital noise cannot be removed correctly. When a timer/counter is used together

220µPD78214 Sub-SeriesFig. 7-138 Interrupt Request Generation Using External Event CounterCountabletiming ofTM2TM2nn-1n+1ICICI8 to 12 clocks16 clocks

- xiv -Contents11-1 Format of External Interrupt Mode Register 0 (INTM0) ...29411-2 Format o

221Chapter 7 Timer/Counter Units7Fig. 7-140 How to Distinguish Input of No Valid Edge from Input of Only One Valid Edgewith External Event Counter(a

222µPD78214 Sub-Series(3) With an in-circuit emulator, digital noise cannot be removed correctly. When the timer/counter is usedtogether with edge de

223Chapter 7 Timer/Counter Units7Fig. 7-141 Interrupt Generation Timing Change by an Erroneously Detected EdgeTMn count value(n = 1,2)For PD78214

224µPD78214 Sub-Series(c) Event counter function (with only 8-bit timer/counter 2)An erroneously detected edge causes no change in the value of the ti

2258CHAPTER 8 A/D CONVERTERThe µPD78214 contains an analog-to-digital (A/D) converter with eight multiplexed analog input pins (AN0 throughAN7).This

226µPD78214 Sub-SeriesFig. 8-1 A/D Converter ConfigurationSuccessive approximationregister (SAR)Sample and hold circuitSeries resistor stringInput se

227Chapter 8 A/D Converter8Cautions 1. To prevent malfunction due to noise, insert a capacitor between each analog input pins (AN0 through AN7) and

228µPD78214 Sub-Series(7) Edge detectorThe edge detector detects the valid edge of an input at the interrupt request input pin (INTP5) and generatesan

229Chapter 8 A/D Converter8Fig. 8-3 A/D Converter Mode Register (ADM) FormatNote FCLK: System clock frequency7 6543210TRG 0 FRCSADM ANI2 ANI1 ANI

230µPD78214 Sub-Series8.3 OPERATION8.3.1 Basic A/D Converter Operation(1) A/D conversion sequenceThe A/D converter operates as follows:(a) The input

- xv -Contents13-1 Format of the Memory Expansion Mode Register (MM) ...34613-2 Format of Prog

231Chapter 8 A/D Converter8A/D conversion continues until the CS bit is reset by software.If data is written to the ADM register during conversion,

232µPD78214 Sub-Series(3) A/D conversion timeThe time required for A/D conversion is determined by the system clock frequency (fCLK) and the FR bit of

233Chapter 8 A/D Converter88.3.3 Scan ModeIn the scan mode, signals input from the analog input pins, specified by bits 1 through 3 (ANI0 through A

234µPD78214 Sub-Series2. If the ADM register is set after registers related to interrupts have been set during the scan mode, an unwanted interrupt ma

235Chapter 8 A/D Converter8(2) Scan-mode A/D conversionWhen triggered, conversion begins with the signal input to the AN0 pin. When the conversion

236µPD78214 Sub-SeriesFig. 8-10 Example of Malfunction in a Hardware-Started A/D ConversionNotes 1. When the operation is normal, the result of conve

237Chapter 8 A/D Converter8Fig. 8-11 Select-Mode A/D Conversion Started by HardwareANn ANn ANn ANnANnANm ANmANmANnANnANnINTP5 pin input(rising edge

238µPD78214 Sub-SeriesFig. 8-12 Scan-Mode A/D Conversion Started by HardwareAN0AN2AN1AN0AN0 AN1 AN2AN1AN0AN1AN0AN0AN0AN2AN1AN0ADCRAN0ADM writingCS←1,

239Chapter 8 A/D Converter88.4 INTERRUPT REQUEST FROM THE A/D CONVERTERThe A/D converter generates an A/D conversion end interrupt request (INTAD),

240µPD78214 Sub-Series(2) About hardware-started A/D conversion(a) Eight to twelve system clocks are required from when a valid edge appears at the IN

- xvi -Contents17-1 Timing Chart for PROM Write and Verify ... 40017-

241Chapter 8 A/D Converter8Fig. 8-14 Example of Malfunction in a Hardware-Started A/D ConversionNotes 1. When the operation is normal, the result o

242

2439CHAPTER 9 ASYNCHRONOUS SERIAL INTERFACEThe µPD78214 contains an asynchronous serial interface, UART (Universal Asynchronous Receiver Transmitter)

244µPD78214 Sub-SeriesFig. 9-1 Asynchronous Serial Interface ConfigurationINTSTInternal busReception bufferRESETTXS1/81/8RXBPE FE OVEINTSRINTSER(ASIS

245Chapter 9 Asynchronous Serial Interface9(1) Reception buffer (RXB)The reception buffer holds the receive data. Each time the shift register rece

246µPD78214 Sub-SeriesFig. 9-2 Format of the Asynchronous Serial Interface Mode Register (ASIM)Cautions 1. The asynchronous serial interface mode reg

247Chapter 9 Asynchronous Serial Interface9Fig. 9-3 Format of the Asynchronous Serial Interface Status Register (ASIS)Caution Be sure to read the r

248µPD78214 Sub-Series• Odd parityIn contrast to even parity, the parity bit for odd parity is controlled so that the number of 1 bits in the transmit

249Chapter 9 Asynchronous Serial Interface99.3.4 ReceptionWhen the RXE bit of the asynchronous serial interface mode register (ASIM) is set to 1, r

250µPD78214 Sub-SeriesTable 9-1 Causes of Reception ErrorsParity errorFraming errorOverrun errorThe parity of the receive data does not match the typ

- xvii -ContentsLIST OF TABLESTable No. Title, Page2-1 Port 2 Functions ...

251Chapter 9 Asynchronous Serial Interface99.4 BAUD RATE GENERATOR9.4.1 Configuration of the Baud Rate Generator for UARTFig. 9-8 shows the config

252µPD78214 Sub-SeriesFig. 9-9 Baud Rate Generator Control Register (BRGC) Format76543210BRGC CETPS2 TPS1 TPS0 MDL3 MDL2 MDL1 MDL0MDL3 MDL2 MDL1 MDL0

253Chapter 9 Asynchronous Serial Interface99.4.3 Operation of the Baud Rate Generator for UARTThe baud rate generator for UART starts operating, wh

254µPD78214 Sub-Series9.5 BAUD RATE SETTINGThe baud rate can be set by three methods listed in Table 9-2.The table indicates the ranges of baud rates

255Chapter 9 Asynchronous Serial Interface9Table 9-3 Example of Setting the BRGC Register When the Baud Rate Generator for UART Is Used—FCHF9HE9HD9

256µPD78214 Sub-Series9.5.2 Example of Setting the Baud Rate When 8-bit Timer/Counter 3 Is UsedTable 9-4 lists examples of setting the baud rate when

257Chapter 9 Asynchronous Serial Interface9Table 9-4 Example of Setting the Baud Rate When 8-Bit Timer/Counter 3 Is Used (Asynchronous Serial Inter

258µPD78214 Sub-Series9.5.3 Example of Setting the BRGC When the External Baud Rate Input (ASCK) Is UsedTable 9-5 lists examples of setting the BRGC

25910CHAPTER 10 CLOCK SYNCHRONOUS SERIAL INTERFACE10.1 FUNCTIONThe clock synchronous serial interface of the µPD78214 is configured as shown in Fig.

260µPD78214 Sub-SeriesFig. 10-1 Block Diagram of the Clock Synchronous Serial InterfaceInternal busDCLS1 CLS0fCLK/32fCLK/88-bit timer/counter 3 outpu

- xviii -Contents8-1 Modes Generating the INTAD...

261Chapter 10 Clock Synchronous Serial Interface10(1) Shift register (SIO)Converts 8-bit serial data into 8-bit parallel data and vice versa. The S

262µPD78214 Sub-Series10.3 CONTROL REGISTERS10.3.1 Clock Synchronous Serial Interface Mode Register (CSIM)This 8-bit register specifies a serial int

263Chapter 10 Clock Synchronous Serial Interface1010.3.2 Serial Bus Interface Control Register (SBIC)The SBIC register consists of bits that contro

264µPD78214 Sub-SeriesFig. 10-3 Format of Serial Bus Interface Control Register (SBIC)★SBIC BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT76543210RELT Trigg

265Chapter 10 Clock Synchronous Serial Interface1010.4 OPERATIONS IN THE THREE-WIRE SERIAL I/O MODEIn three-wire serial I/O mode, the device can co

266µPD78214 Sub-SeriesFig. 10-5 Timing in Three-Wire Serial I/O ModeNotes Master CPU : OutputSlave CPU : InputIn three-wire serial I/O mode, the SO

267Chapter 10 Clock Synchronous Serial Interface1010.4.2 Operation When Only Transmission Is PermittedTransmission is enabled when the CTXE bit of

268µPD78214 Sub-Series(1) Selecting the internal clock as the serial clockWhen transmission and reception are started, the serial clock is output from

269Chapter 10 Clock Synchronous Serial Interface10(2) Function to select a chip by its addressThe master sends an address to select a slave chip.(3)

270µPD78214 Sub-Series10.5.2 Configuration of the Serial InterfaceFig. 10-9 is a block diagram of the µPD78214.The serial clock pin (SCK) and serial

Cautions on CMOS Devices1 Countermeasures against static electricity for all MOSsCaution When handling MOS devices, take care so that they are not ele

11CHAPTER 1 GENERALThe µPD78214 sub-series is part of the 78K/II series of eight-bit single-chip microcomputers capable of accessingan expanded memor

271Chapter 10 Clock Synchronous Serial Interface10Fig. 10-9 Block Diagram of Clock Synchronous Serial InterfaceInternal busDCLS1 CLS0fCLK/32fCLK/8I

272µPD78214 Sub-Series10.5.3 Detecting an Address MatchSBI communication is started when a slave device is selected according to the address sent by

273Chapter 10 Clock Synchronous Serial Interface10Fig. 10-10 Format of Clock Synchronous Serial Interface Mode Register (CSIM)Caution Do not change

274µPD78214 Sub-Series(2) Serial bus interface control register (SBIC)This 8-bit register consists of bits controlling the serial bus statuses and fla

275Chapter 10 Clock Synchronous Serial Interface10Fig. 10-11 Format of SBIC Register (2/2)Remarks (R) : Read-only(W) : Write-only(R/W): Read/wri

276µPD78214 Sub-Series(3) Shift register (SIO)This 8-bit shift register is used for parallel-serial conversion.The data written into the SIO is output

277Chapter 10 Clock Synchronous Serial Interface1010.6 SBI COMMUNICATION AND SIGNALSThis section describes the format of the SBI serial data and s

278µPD78214 Sub-Series10.6.2 Command Signal (CMD)The command signal is the SB0 line going from high to low while the SCK line is high (the serial clo

279Chapter 10 Clock Synchronous Serial Interface1010.6.4 Command and DataThe master device sends commands to, and sends or receives data to or from

280µPD78214 Sub-Series10.6.6 Busy Signal (BUSY) and Ready Signal (READY)The busy signal informs the master device that the slave device is preparing

2µPD78214 Sub-Series78K/II ProductsThe following are contained: A/D converter D/A converterThe PWM output function is added.The macro service an

281Chapter 10 Clock Synchronous Serial Interface10Fig. 10-23 ACKT OperationCaution Do not set ACKT before transfer has been completed.Fig. 10-24 A

282µPD78214 Sub-Series(d) When ACKE is set to 1 for a short period of timeFig. 10-25 ACKD Operations(a) When the ACK signal is output during the ni

283Chapter 10 Clock Synchronous Serial Interface10Fig. 10-26 BSYE OperationSCKSB0BSYE9BUSY876ACKWhen BSYE = 1 at this point When reset operation is

284µPD78214 Sub-SeriesTable 10-2 Signals in SBI Mode (1/3)SCKSB0“H”“H”SCKSB0Rising edge of SB0while SCK is set to 1Falling edge of SB0while SCK is se

285Chapter 10 Clock Synchronous Serial Interface10Table 10-2 Signals in SBI Mode (2/3)Low signal output to SB0 within a single cycle of the SCK clo

286µPD78214 Sub-SeriesTable 10-2 Signals in SBI Mode (3/3)Notes 1. If WUP is set to 0, CSIIF is always set at the rising edge of the eighth pulse of

287Chapter 10 Clock Synchronous Serial Interface1010.6.8 CommunicationIn SBI communication, the master device outputs an address on the serial bus

288µPD78214 Sub-SeriesFig. 10-27 Sending an Address from Master Device to Slave DeviceProgram processingHardware operationProgram processingSCK pin12

289Chapter 10 Clock Synchronous Serial Interface10Fig. 10-28 Sending a Command from Master Device to Slave DeviceProgram processingHardware operati

290µPD78214 Sub-SeriesFig. 10-29 Sending Data from Master Device to Slave DeviceProgram processingHardware operationProgram processingSCK pin12345678

3Chapter 1 General11.1 FEATURES°78K/II series°Multiplexed internal bus (faster execution of instructions)Minimum instruction cycle (operating at 12

291Chapter 10 Clock Synchronous Serial Interface10Fig. 10-30 Sending Data from the Slave Device to the Master DeviceProgram processingHardware oper

292µPD78214 Sub-Series10.7 NOTES(1) Do not change CTXE from 0 to 1 and CRXE from 1 to 0, or vice versa, by means of a single instruction. If thisis

29311CHAPTER 11 EDGE DETECTION FUNCTIONPins P20 to P26 support an edge detection function to program a rising or falling edge. The detected edge is

294µPD78214 Sub-SeriesFig. 11-1 Format of External Interrupt Mode Register 0 (INTM0)ES217ES206ES115ES104ES013ES00201ESNMI0INTM0ES01Falling edgeSpecif

295Chapter 11 Edge Detection Function11Fig. 11-2 Format of External Interrupt Mode Register 1 (INTM1)0706ES515ES504ES413ES402ES311ES300INTM1ES31Fal

296µPD78214 Sub-Series11.2 EDGE DETECTION ON PIN P20An edge on pin P20 is detected after noise elimination by means of analog delay. A pulse width o

297Chapter 11 Edge Detection Function1111.3 EDGE DETECTION ON PINS P21 TO P26An edge on pins P21 to P26 is detected after digital noise elimination

298µPD78214 Sub-Series(b) Erroneously detected edge during input of a high signalINTPn input (n = 0 to 6)Erroneously detected edgefCLK/4After noise r

299Chapter 11 Edge Detection Function11(5) If noise input to pins P21 to P26 is synchronized with the fCLK/4 clock of the µPD78214, it may not be ju

300µPD78214 Sub-Series• Compare operation of the timer/counter : If the mode for carrying out a clear operation after a captureoperation is selected,

4µPD78214 Sub-Series1.2 ORDERING INFORMATION AND QUALITY GRADE1.2.1 Ordering InformationOrdering code Package Internal ROMµPD78212CW-××× 64-pin plas

30112CHAPTER 12 INTERRUPT FUNCTIONSThe µPD78214 has the following two interrupt handling modes. Either mode can be selected by the program.Interrupt

302µPD78214 Sub-Series12.1 INTERRUPT REQUEST SOURCESThe µPD78214 has 19 interrupt request sources shown in Table 12-2. Each of these sources is assi

303Chapter 12 Interrupt Functions1212.1.2 Nonmaskable Interrupt RequestA nonmaskable interrupt request is input to the NMI pin. When a valid edge,

304µPD78214 Sub-Series(2) Selecting INTP5 or INTADInterrupt INTP5 or INTAD is selected by the A/D converter mode register (ADM). (Either of these int

305Chapter 12 Interrupt Functions12Table 12-3 Flags for Interrupt Request SourcesINTP0INTP1INTP2INTP3INTC00INTC01INTC10INTC11INTC21INTP4INTC30INTP5

306µPD78214 Sub-Series12.2.2 Interrupt Mask Register (MK0)The MK0 register is a 16-bit register consisting of interrupt mask flags. Each interrupt m

307Chapter 12 Interrupt Functions12When a low-priority vectored interrupt is being handled, vectored interrupt requests with lower and higherpriorit

308µPD78214 Sub-Series12.2.6 Program Status Word (PSW)The PSW is a register that holds the result of instruction execution and the current status of

309Chapter 12 Interrupt Functions12Resetting the NMIS bit to 0 during execution of a nonmaskable interrupt service program enables multiple-interrup

310µPD78214 Sub-Series(c) If a new NMI request occurs during execution of an NMI service program (when the NMIS bit is reset to 0 bythe current NMI se

5Chapter 1 General11.2.2 Quality GradeOrdering code Package Quality gradeµPD78212CW-××× 64-pin plastic shrink DIP (750 mil) StandardµPD78212GC-×××-

311Chapter 12 Interrupt Functions123. Nonmaskable interrupts are always accepted except during execution of the nonmaskable interrupt handling progr

312µPD78214 Sub-SeriesFig. 12-10 Interrupt Handling AlgorithmInterrupts for ××PR = 0 occur simultaneously?××IF = 1?××MK = 0?××PR = 0?Yes (interrupt r

313Chapter 12 Interrupt Functions1212.3.4 Multiple-Interrupt HandlingThe µPD78214 performs multiple-interrupt handling in which another interrupt r

314µPD78214 Sub-SeriesFig. 12-11 Example of Handling an Interrupt Request When an Interrupt Is Already Being Handled (1/2)Main routineProcessing aVec

315Chapter 12 Interrupt Functions12Fig. 12-11 Example of Handling an Interrupt Request When an Interrupt Is Already Being Handled (2/2)Main routine

316µPD78214 Sub-SeriesFig. 12-12 Example of Handling Interrupts That Occur Simultaneously12.3.5 Interrupt Request and Macro Service PendingWhen any

317Chapter 12 Interrupt Functions12Example of correct coding (2)LOOP: BT IF0H.3, $NEXTBR $LOOPNEXT: ←2. In addition, when you have to use a codi

318µPD78214 Sub-Series3. “Peripheral RAM” corresponds to the internal RAM at addresses 0FC80H through 0FDFFH (for the µPD78212, 0FD80H through0FDFFH).

319Chapter 12 Interrupt Functions1212.4 MACRO SERVICE FUNCTION12.4.1 Macro Service OutlineMacro service is one of the interrupt handling methods.

320µPD78214 Sub-Series12.4.2 Macro Service TypesThe macro service can be used by the 17 types of interrupts listed in Table 12-7 (of which, 15 types

6µPD78214 Sub-Series1.3 PIN CONFIGURATION (TOP VIEW)1.3.1 Normal Operating Mode(1) 64-pin plastic shrink DIP, 64-pin plastic QUIP, 64-pin ceramic sh

321Chapter 12 Interrupt Functions12(3) Type CTransfers 1-byte data from memory to the real-time output port and the compare register for 8-bit timer

322µPD78214 Sub-Series12.4.4 Macro Service Control Register(1) Macro service control wordThe macro service function of the µPD78214 is controlled usi

323Chapter 12 Interrupt Functions12(2) Macro service mode registerA macro service mode register is an 8-bit register that specifies the mode of macr

324µPD78214 Sub-SeriesTable 12-8 Interrupt Requests That Can Specify Macro Service and Related SFRs (Type A)Interrupt request specifyingthe type A ma

325Chapter 12 Interrupt Functions12Fig. 12-18 Flow of Data Transfer by Macro Service (Type A)Accepts macro service requestRead contents of macro se

326µPD78214 Sub-Series(2) Macro service channel configurationA channel pointer and a macro service counter (MSC) specify the addresses of transfer sou

327Chapter 12 Interrupt Functions12(3) Example of using the type A macro serviceThe following example shows how data received through an asynchronou

328µPD78214 Sub-SeriesFig. 12-21 Flow of Data Transfer by Macro Service (Type B)Accepts macro service requestRead contents of macro service mode regi

329Chapter 12 Interrupt Functions12(2) Macro service channel configurationThe macro service pointer (MP) indicates a data buffer area in the 64K mem

330µPD78214 Sub-Series(3) Example of using the type B macro serviceThe following example shows how parallel data is input from port 3 in synchronizati

7Chapter 1 General1(2) 68-pin plastic QFJRemark The NC pin is not connected inside the chip.1011121314151617181920212223242526P70/AN0P34/TO0P35/TO1

331Chapter 12 Interrupt Functions1212.4.7 Macro Service Type C(1) OperationThe type C macro service controls 8-bit timer/counter 1 and the real-tim

332µPD78214 Sub-SeriesFig. 12-25 Flow of Data Transfer by Macro Service (Type C)Accepts macro service requestRead contents of macro service mode regi

333Chapter 12 Interrupt Functions12Ring control?Decrement ring counterRing counter = 0?Vectored interrupt request occursNoNoYesNoSubtract modulo reg

334µPD78214 Sub-Series(2) Macro service channel configurationThere are two types of type C macro service channels, as shown in Fig. 12-26.The timer ma

335Chapter 12 Interrupt Functions12(b) With ring controlModulo register(MR)Ring counter(RC)Macro service counter(MSC)Data macro service pointer,low

336µPD78214 Sub-Series(3) Example of using the type C macro serviceThe following example shows a pattern output to the real-time output port and how t

337Chapter 12 Interrupt Functions12Fig. 12-28 Data Transfer Control Timing(4) Example of using automatic addition control and ring control(a) Autom

338µPD78214 Sub-SeriesFig. 12-29 Four-Phase Stepping Motor with Phase 1 ExcitationFig. 12-30 Four-Phase Stepping Motor with Phases 1 and 2 Excitatio

339Chapter 12 Interrupt Functions12Fig. 12-31 Block Diagram 1 for Automatic Addition Control Plus Ring Control(Constant-Speed Rotation with Phases 1

340µPD78214 Sub-SeriesFig. 12-32 Timing Chart 1 for Automatic Addition Control Plus Ring Control(Constant-Speed Rotation with Phases 1 and 2 Excitatio

8µPD78214 Sub-Series(3) 64-pin plastic QFP (14 × 14 mm)12345678910111213141516P64/RDP63/A19P62/A18P61/A17P60/A16RESETX2X1VSSP57/A15P56/A14P55/A13P54/A

341Chapter 12 Interrupt Functions12Fig. 12-33 Block Diagram 2 for Automatic Addition Control Plus Ring Control(with the Output Timing Varied by Phas

342µPD78214 Sub-SeriesFig. 12-34 Timing Chart 2 for Automatic Addition Control Plus Ring Control(with the Output Timing Varied by Phase 2 Excitation)∆

343Chapter 12 Interrupt Functions1212.5 NOTES(1) Do not use the RETI instruction to return from the software interrupt.(2) A macro service request

344µPD78214 Sub-SeriesExample of correct coding (2)LOOP: BT IF0H.3, $NEXTBR $LOOPNEXT: ←(6) In addition, when you have to use a coding of the instruct

34513CHAPTER 13 LOCAL BUS INTERFACE FUNCTIONThe local bus interface function is provided to connect external memories (ROM and RAM) and I/Os.External

346µPD78214 Sub-Series13.1 CONTROL REGISTERS13.1.1 Memory Expansion Mode Register (MM)The MM register is an 8-bit register for controlling externall

347Chapter 13 Local Bus Interface Function1313.1.2 Programmable Wait Control Register (PW)The PW register is an 8-bit register for specifying the n

348µPD78214 Sub-SeriesFig. 13-3 Read TimingHigher addressLower address(output)Data (input)Hi-Z Hi-ZA8-A15(output)AD0-AD7ASTB (output)RD (output)Hi-ZF

349Chapter 13 Local Bus Interface Function13Fig. 13-5 Accessing Expansion Data Memory(a) Read cycleRD (output)A16-A19(output)Contents of P6/PM6 re

350µPD78214 Sub-Series13.2.3 Memory Mapping with Expanded MemoryFigs. 13-6 to 13-9 show the memory maps when the memory has been expanded. Even when

9Chapter 1 General1(4) 74-pin plastic QFP (20 × 20 mm)Remark The NC pins are not connected inside the chip.P65/WRP66/WAIT/AN6P67/REFRQ/AN7P07NCP06P

351Chapter 13 Local Bus Interface Function13Fig. 13-6 Data Memory Expansion for µPD78212 (When EA = L)Internal RAMExternal SFR areaSFR0FD7FH0FD80H0

352µPD78214 Sub-SeriesFig. 13-7 Data Memory Expansion for µPD78212 (When EA = H)Internal RAMExternal SFR areaSFRExternal memoryInternal RAMExternal S

353Chapter 13 Local Bus Interface Function13Fig. 13-8 Data Memory Expansion for µPD78213 and µPD78214 (When EA = L)Internal RAMExternal SFR areaSFR

354µPD78214 Sub-SeriesFig. 13-9 Data Memory Expansion for µPD78214 and µPD78P214 (When EA = H)Internal RAMExternal SFR areaSFRExternal memoryInternal

355Chapter 13 Local Bus Interface Function1313.2.4 Example of Connecting MemoriesFig. 13-10 shows an example of connecting memories to the µPD78214

356µPD78214 Sub-SeriesFig. 13-10 Example of Connecting Memories to µPD78214PD23C4000AµPD43256AC-12µPD27C512D-15µLED0-D7OEQ0-Q7AD0-AD7ASTBA8-A14OECEA1

357Chapter 13 Local Bus Interface Function1313.3 INTERNAL ROM HIGH-SPEED FETCH FUNCTIONThe µPD78212, µPD78214, and µPD78P214 contain an internal RO

358µPD78214 Sub-SeriesFig. 13-11 Wait Control Space of µPD78212 (When EA = L)Internal RAMExternal SFR areaSFR0FD7FHExpansion datamemory00000HExternal

359Chapter 13 Local Bus Interface Function13Fig. 13-12 Wait Control Space of µPD78212 (When EA = H)Internal RAMExternal SFR areaSFR0FD7FHExpansion

360µPD78214 Sub-SeriesFig. 13-13 Wait Control Space of µPD78213 and µPD78214 (When EA = L)Internal RAMExternal SFR areaSFR0FCFFHExpansion datamemory0

10µPD78214 Sub-SeriesP00-P07 : Port 0P20-P27 : Port 2P30-P37 : Port 3P40-P47 : Port 4P50-P57 : Port 5P60-P67 : Port 6P70-P75 : Port 7TO0-TO3 : Timer o

361Chapter 13 Local Bus Interface Function13Fig. 13-14 Wait Control Space of µPD78214 and µPD78P214Internal RAMExternal SFR areaSFR0FCFFHExpansion

362µPD78214 Sub-SeriesFig. 13-15 Read Timing of Programmable Wait Function (1/2)(a) When zero wait states are setHigher addressLoweraddress(output)D

363Chapter 13 Local Bus Interface Function13Fig. 13-15 Read Timing of Programmable Wait Function (2/2)(c) When two wait states are setHigher addre

364µPD78214 Sub-SeriesFig. 13-16 Write Timing of Programmable Wait Function (1/2)(a) When zero wait states are setHigher addressLoweraddressDataHi-Z

365Chapter 13 Local Bus Interface Function13Fig. 13-16 Write Timing of Programmable Wait Function (2/2)(c) When two wait states are setHigher addr

366µPD78214 Sub-SeriesFig. 13-17 Timing When External Wait Signal Is Used(a) Read timingHigher addressLoweraddress(output)Data (input)Hi-Z Hi-ZA8-A1

367Chapter 13 Local Bus Interface Function1313.5 PSEUDO STATIC RAM REFRESH FUNCTION13.5.1 FunctionThe µPD78214 provides the pseudo static RAM refr

368µPD78214 Sub-Series13.5.3 Operation(1) Pulse refresh operationTo support the pulse refresh cycle of pseudo static RAM, the REFRQ pin outputs refre

369Chapter 13 Local Bus Interface Function13(b) Accessing External MemoryThe refresh bus cycle is generated at the intervals specified with the refr

370µPD78214 Sub-Series(2) Self-refreshSelf-refresh is performed to retain the contents of pseudo static RAM when in standby mode.(a) Setting self-refr

The information in this document is subject to change without notice.No part of this document may be copied or reproduced in any form or by any means

11Chapter 1 General11.3.2 PROM Programming Mode (P20/NMI = 12.5 V, RESET = L)(1) 64-pin plastic shrink DIP, 64-pin plastic QUIP, 64-pin ceramic shr

371Chapter 13 Local Bus Interface Function13Caution If the RFEN bit of the refresh mode register (RFM) is already set to 1 (or is simultaneously set

372µPD78214 Sub-Series13.5.4 Example of Connecting Pseudo Static RAMFig. 13-23 shows an example of connecting pseudo static RAM to the µPD78214. In

373Chapter 13 Local Bus Interface Function13(3) When macro service Type A or Type C is used in external memory expansion mode (the µPD78213 always u

374µPD78214 Sub-SeriesFig. 13-24 Return from Self-RefreshClear RFEN bit to 0Set RFLV bit to 1Set RFEN bit to 1Approximately 200 ns delayRFLV = 1YesN

375Chapter 13 Local Bus Interface Function13Fig. 13-27 Preventing Problems That May Occur during EmulationA19To target circuitA18A17A16ASTBQ4Q3Q2Q1

376

37714CHAPTER 14 STANDBY FUNCTION14.1 FUNCTION OVERVIEWThe µPD78214 supports a standby function to reduce the system’s power consumption. With the s

378µPD78214 Sub-SeriesFig. 14-2 Standby Function BlockSystem clock oscillatorFrequency dividerOscillation settling time counter (16 bits)fxx orfx fCL

379Chapter 14 Standby Function1414.2 STANDBY CONTROL REGISTER (STBC)The standby control register (STBC) is an 8-bit register which controls standby

380µPD78214 Sub-Series14.3.2 Releasing HALT ModeHALT mode can be released by any of the following three sources:• Nonmaskable interrupt request (NMI)

12µPD78214 Sub-Series(2) 68-pin plastic QFJCaution The symbols enclosed in parentheses indicate that the corresponding pins, not used in PROM programm

381Chapter 14 Standby Function14(2) Release by a maskable interrupt requestOnly maskable interrupts with 0 in the interrupt mask flag can be used to

382µPD78214 Sub-Series14.4 STOP MODE14.4.1 Specifying STOP Mode and Operation States in STOP ModeThe system enters STOP mode when the STP bit of the

383Chapter 14 Standby Function14Fig. 14-4 Releasing STOP Mode with an NMI SignalCaution If another effective edge of the NMI signal is detected dur

384µPD78214 Sub-Series14.4.3 Notes on Using STOP ModeCheck the following items to ensure that current consumption is appropriately reduced in STOP mo

385Chapter 14 Standby Function14Fig. 14-6 Example of Address Bus ArrangementPower supply backed upVDD VDDVSS VSSINDiode with small VFAn(n = 8 to 15

386µPD78214 Sub-SeriesFig. 14-8 Example Arrangement for Analog Input PinVDDVSSANn (n = 0 to 7)Power supply backed upPD78214µAVREFDiode with small VFP

387Chapter 14 Standby Function14Fig. 14-9 Example of Longer Oscillation Settling TimeNMI (effective at falling edge)216/fCLKSTOP mode Wait for osci

388

38915CHAPTER 15 RESET FUNCTION15.1 RESET FUNCTIONWhen the signal applied to the RESET input pin is low, the system is reset, and each hardware compo

390µPD78214 Sub-SeriesTable 15-1 Pin States during Reset and After Reset State Is ReleasedPin nameP00-P07P20/NMI-27/SIP30/RxD-P37/TO3P40/AD0-P47/AD7P

13Chapter 1 General1(3) 64-pin plastic QFP (14 × 14 mm)Caution The symbols enclosed in parentheses indicate that the corresponding pins, not used in

391Chapter 15 Reset Function15Table 15-2 Hardware States after Reset (1/2)State after resetHardwareProgram counter (PC)Stack pointer (SP)Program st

392µPD78214 Sub-SeriesTable 15-2 Hardware States after Reset (2/2)State after resetHardwareMode register (CSIM)Shift register (SIO)Asynchronous mode

393Chapter 15 Reset Function15Fig. 15-3 Timing Charts for Reset Operation(a) For µPD78213(b) For µPD7821415.2 NOTEWhen resetting the system at p

394

39516CHAPTER 16 APPLICATION EXAMPLES16.1 OPEN-LOOP CONTROL OF STEPPER MOTORSThis section provides an example of controlling stepper motors with the

396µPD78214 Sub-SeriesFig. 16-1 Example of Controlling Two Stepper MotorsInternal busInternal busCompare registerCR118-bit timer 1TM1Buffer registerP

397Chapter 16 Application Examples1616.2 SERIAL COMMUNICATION WITH MULTIPLE DEVICESFig. 16-2 shows an example of a system configured with a serial

398µPD78214 Sub-SeriesFig. 16-3 Example of Communication with SBIAddress Command CommandSB0Address Command Data CommandSB0Address Command Data DataSB

39917CHAPTER 17 PROGRAMMING FOR THE µPD78P214The µPD78P214 employs an electrically writable PROM of 16384 × 8 bits for program memory. Use the NMI a

400µPD78214 Sub-SeriesFig. 17-1 Timing Chart for PROM Write and VerifyHi-ZData inputA0-A14Data outputData inputHi-Z Hi-ZHi-Z+12.5 VD0-D7VDDVpp+6 VVDD

14µPD78214 Sub-Series(4) 74-pin plastic QFP (20 × 20 mm)Caution The symbols enclosed in parentheses indicate that the corresponding pins, not used in

401Chapter 17 Programming for The µPD7821417Fig. 17-2 Write Operation Flowchart17.3 PROCEDURE FOR READING FROM PROMThe contents of PROM can be rea

402µPD78214 Sub-SeriesFig. 17-3 PROM Read Timing ChartAddress inputA0-A14Hi-ZData outputCE (input)OE (input)D0-D7Hi-Z17.4 NOTEWhen VPP is +12.5 V an

40318CHAPTER 18 INSTRUCTION OPERATIONSThis chapter describes the operation of each instruction of the µPD78214 sub-series. Refer to the 78K/II Serie

404µPD78214 Sub-Seriessaddr, saddr’ : Memory address indicated in short direct addressing mode;FE20H-FF1FH immediate data or labelsaddrp : Memory addr

405Chapter 18 Instruction Operations18Z : Zero flagRBS1-RBS0 : Register bank selection flagIE : Interrupt request enable flagSTBC : Standby control

406µPD78214 Sub-SeriesMOVXCHOperationMnemonic OperandNo. ofbytesFlagsZACCY18.2 LIST OF OPERATIONS(1) 8-bit data transfer instructions: MOV, XCHr, #b

407Chapter 18 Instruction Operations18MOVWOperationMnemonic OperandNo. ofbytesFlagsrp, #word 3 rp ← wordsaddrp, #word 4 (saddrp) ← wordsfrp, #word 4

408µPD78214 Sub-SeriesSUBSUBCANDOROperationMnemonic OperandNo. ofbytesFlagsA, #byte 2 A, CY ← A – byte × × ×saddr, #byte 3 (saddr), CY ← (saddr) – by

409Chapter 18 Instruction Operations18XORCMPOperationMnemonic OperandNo. ofbytesFlagsA, #byte 2 A ← A ∨ byte ×saddr, #byte 3 (saddr) ← (saddr) ∨ byt

410µPD78214 Sub-SeriesRORROLRORCROLCSHRSHLSHRWSHLWROR4ROL4OperationMnemonic OperandNo. ofbytesFlagsr, n 2 (CY, r7 ← r0, rm-1 ← rm) × n times n=0 to 7

15Chapter 1 General1VPP: Programming power supplyRESET : ResetD0-D7 : Data busA0-A14 : Address busVSS: GroundOE : Output enableVDD: Power supplyCE :

411Chapter 18 Instruction Operations18ADJBAADJBSOperationMnemonic OperandNo. ofbytesFlagsZACCY1Use the decimal adjust accumulator after addition.××

412µPD78214 Sub-SeriesXOR1SET1CLR1NOT1OperationMnemonic OperandNo. ofbytesFlagsZACCYCY, saddr.bit 3 CY ← CY ∨ (saddr.bit) ×CY, sfr.bit 3 CY ← CY ∨ sfr

413Chapter 18 Instruction Operations18CALLCALLFCALLTBRKRETRETIRETBOperationMnemonic OperandNo. ofbytesFlagsZACCY!addr16 3 (SP – 1) ← (PC + 3)H, (SP

414µPD78214 Sub-SeriesBCBLBNCBNLBZBEBNZBNEBTBFBTCLRDBNZOperationMnemonic OperandNo. ofbytesFlags$ addr16 2 PC ← PC + 2 + jdisp8 if CY = 1addr16 2 PC ←

415Chapter 18 Instruction Operations18MOVSELNOPEIDIOperationMnemonic OperandNo. ofbytesFlagsSTBC, #byte 4 STBC ← byteRBn 2 RBS1 – 0 ← n, n = 0 – 31

416µPD78214 Sub-SeriesFirstoperandSecondoperand# byte Asfr mem & mem!addr16& !addr16PSW nNoneNote 2rr'saddrsaddr'MOVXCHMOVXCHADDNote

417Chapter 18 Instruction Operations18(2) 16-bit instructionsMOVW, ADDW, SUBW, CMPW, INCW, DECW, SHRW, and SHLWTable 18-2 16-Bit Instructions for E

418µPD78214 Sub-Series(3) Bit manipulation instructionsMOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BT, BF, and BTCLRTable 18-3 Bit Manipulation Instruct

419Chapter 18 Instruction Operations18(4) Call instructions and branch instructionsCALL, CALLF, CALLT, BR, BC, BT, BF, BTCLR, DBNZ, BL, BNC, BNL, BZ

420

16µPD78214 Sub-Series1.4 EXAMPLE APPLICATION SYSTEM (PRINTER)M P00-P03M P04-P07TOSCKSOTXDRXDPortsAVREFAVSSAN0AN1AN2-AN7Temperature sensorMotor supply

421AAPPENDIX A 78K/II SERIES PRODUCT LISTThe following pages list the 78K/II series products.For details, refer to each User’s Manual.

422µPD78214 Sub-SeriesSeries nameµPD78214 Sub-SeriesµPD78218A Sub-SeriesµPD78224 Sub-SeriesµPD78214(µPD78P214)Number of basic instructionsMinimum inst

423Appendix A 78K/II Series Product ListA(1/3)µPD78234 Sub-SeriesµPD78244 Sub-SeriesµPD78233µPD78243µPD78238(µPD78P238)µPD78237500 ns 333 ns 333 ns5

424µPD78214 Sub-SeriesSeries nameµPD78214 Sub-SeriesµPD78218A Sub-SeriesµPD78224 Sub-SeriesµPD78214(µPD78P214)PWM outputComparatorµPD78213µPD78212µPD7

425Appendix A 78K/II Series Product ListA(2/3)µPD78234 Sub-SeriesµPD78244 Sub-SeriesµPD78233µPD78243µPD78238(µPD78P238)µPD78237None8 bits × 8µPD7823

426µPD78214 Sub-SeriesSeries nameµPD78214 Sub-SeriesµPD78218A Sub-SeriesµPD78224 Sub-SeriesµPD78214(µPD78P214)InterruptµPD78213µPD78212µPD78224(µPD78P

427Appendix A 78K/II Series Product ListA(3/3)µPD78234 Sub-SeriesµPD78244 Sub-SeriesµPD78233µPD78243µPD78238(µPD78P238)µPD7823772 levels (programmab

428

429BAPPENDIX B DEVELOPMENT TOOLSThe development tools described on the following pages are available for the development of systems usingµPD78214 sub

430µPD78214 Sub-SeriesIE-78210-R Note 2IE-78240-RIE-78240-R-AIn-circuit emulatorEmulation probeEP-78210CW Note 2EP-78210GC Note 2EP-78210GJEP-78210GQ

17Chapter 1 General11.5 BLOCK DIAGRAMNotes 1. None for µPD78213 and µPD78213(A), 8KB for µPD78212 and µPD78212(A), 16KB for µPD78214, µPD78P214, µP

431Appendix B Development ToolsBIE-78240-R-A The IE-78240-R-A is an enhanced version of the IE-78210-R and IE-78240-R.This in-circuit emulator can b

432µPD78214 Sub-SeriesHARDWARE (2/2)This socket is mounted on the board of the user system developed for the 74-pin QFP. It is used together with the

433Appendix B Development ToolsBB.2 SOFTWAREB.2.1 Language Processing Software (1/3)78K/II series relocatableassembler (RA78K/II)This relocatable

434µPD78214 Sub-SeriesOSµS5A1RA78K2µS5A10RA78K2µS5A13RA78K2µS7B11RA78K2µS7B10RA78K2µS7B13RA78K2µS3H15RA78K2µS3K15RA78K2µS3M15RA78K2Part numberDistribu

435Appendix B Development ToolsBOSµS5A10CC78K2-LµS5A13CC78K2-LµS7B10CC78K2-LµS7B13CC78K2-LµS3H15CC78K2-LµS3K15CC78K2-LµS3M15CC78K2-LPart number5.25-

436µPD78214 Sub-SeriesThis program enables control of the in-circuit emulator for the 78K/II series from thehost machine. It can automatically execut

437Appendix B Development ToolsBThis program provides the serial and parallel interfaces between PG-1500 and thehost machine, enabling the host mach

438µPD78214 Sub-SeriesB.3 UPGRADING OTHER IN-CIRCUIT EMULATORS TO 78K/II SERIES LEVELThe 78K series and 75X series in-circuit emulators can be upgrad

439Appendix B Development ToolsBIE-78112-RNote 1IE-78210-RNote 1IE-78220-RNote 1IE-78130-RIE-78230-RNote 1IE-78310-RNote 1IE-78310A-RIE-75000-RIE-75

440µPD78214 Sub-SeriesIE-78112-RNote 2IE-78220-RNote 2IE-78310-RNote 2IE-78310A-RIE-75000-RIE-75001-RIE-78000-RIE-78130-RIE-78140-RIE-78230-RIE-78230-

18µPD78214 Sub-Series1.6 FUNCTIONSItemInput pinsOutput pinsI/O pinsTotalConnected to apull-up resistorDriving a LEDdirectlyDriving atransistor direct

441CAPPENDIX C SOFTWARE FOR EMBEDDED APPLICATIONSC.1 FUZZY INFERENCE DEVELOPMENT SUPPORT SYSTEMOSµS5A10FE9000µS5A13FE9000µS7B10FE9200µS7B13FE9200Par

442

443DAPPENDIX D REGISTER INDEXD.1 REGISTER INDEX16-bit capture register (CR02) ... 11116-bit compare register (CR00,CR01) ... 11116-bit timer 0 (TM0

444µPD78214 Sub-SeriesPort 3 (P3) ... 66Port 4 (P4) ... 75Port 5 (P5) ... 80Port 6 (P6) ... 84Port 7 (P7) ... 92Port 0 buffer register (P0L, P0H) ...

445Appendix D Register IndexDD.2 REGISTER SYMBOL INDEXAADCR: A/D conversion result register ... 227ADM: A/D converter mode register ... 229, 304ASI

446µPD78214 Sub-SeriesPM0: Port 0 mode register ... 61PM3: Port 3 mode register ... 72PM5: Port 5 mode register ... 80PM6: Port 6 mode register ... 89

447EAPPENDIX E INDEXE.1 INDEX0 parity ... 247, 24816-bit timer 0 ... 111, 11416-bit timer/counter ... 1091M-byte expansion function ... 3484-bit co

448µPD78214 Sub-SeriesClock synchronous serial interface mode register ... 262, 273Command ... 279Command detection flag ... 274Command signal ... 278

449Appendix E IndexEInterrupt status register ... 304, 307Interval timer ... 129, 151, 190, 192, 210, 211Interval ... 109, 139, 159, 205LLocal bus i

450µPD78214 Sub-SeriesPort 3 mode control register ... 72Port 3 mode register ... 71Port 4 ... 75Port 5 ... 80Port 5 mode register ... 80Port 6 ... 84

19Chapter 1 General1ItemA/D converterInterruptInstruction setPackageµPD78213µPD78212µPD78214µPD78P214Eight channels, each having a resolution of eig

451Appendix E IndexESpecial function register ... 43, 50Specifying 1M-byte expansion mode ... 346Specifying the operation of the capture/compare reg

452µPD78214 Sub-SeriesE.2 SYMBOL INDEXAA ... 48A0 ... 31A1 ... 31A2 ... 31A3 ... 31A4 ... 31A5 ... 31A6 ... 31A7 ... 31A8 ... 29, 31, 345A9 ..

453Appendix E IndexECE2 ... 163, 167CE3 ... 207, 208CHT0 ... 323CHT1 ... 323CHT2 ... 323CI ... 28, 161, 170CIF00 ... 305CIF01 ... 305CIF10 ... 305CI

454µPD78214 Sub-SeriesES00 ... 294ES01 ... 294ES10 ... 294ES11 ... 294ES20 ... 294ES21 ... 294ES30 ... 295ES31 ... 295ES40 ... 295, 303ES41 ... 295, 3

455Appendix E IndexEµPD78210 ... 20µPD78212 ... 1µPD78213 ... 1µPD78214 ... 1µPD78p214 ... 1, 399NNC ... 31, 32NMI ... 428, 302, 303NMIS ... 307OOE

456µPD78214 Sub-SeriesPRS2 ... 207PRS3 ... 207PRS10 ... 144PRS11 ... 144PRS12 ... 144PRS20 ... 164PRS21 ... 164PRS22 ... 164PRS23 ... 164PS0 ... 246PS

457Appendix E IndexESO ... 29, 265SO pin ... 267SO latch ... 261SP ... 46Specifying HALT mode ... 379Specifying STOP mode ... 382SRIF ... 305SRISM .

458

20µPD78214 Sub-SeriesProductItemRAM capacityI/O pinsTimer/counterSerial interfaceInterruptA/D converterPackageOthersµPD78213512 bytes• Software progra

Main Revisions in This EditionPage DescriptionP.55 VSS and "Caution" have been added in (a) of Fig.4-2.P.329"Caution" has been add

21Chapter 1 General1Series nameµPD78214 Sub-SeriesµPD78218A Sub-SeriesµPD78214µPD78214(A)µPD78218AProductµPD78212µPD78212(A)µPD78213µPD78213(A)µPD78

22µPD78214 Sub-SeriesProductItemQuality gradePackageStandard• 64-pin plastoc shrink DIP• 64-pin plastic QFP• 74-pin plastic QFPµPD78212µPD78212(A)Spec

23Chapter 1 General1Product nameParameterInternal ROMInternal RAMPort 4Port 5Port 6Others8KB masked ROM at00000H to 01FFFH384 bytes at 0FD80Hto 0FEF

24

252CHAPTER 2 PIN FUNCTIONS2.1 PIN FUNCTION LIST2.1.1 Normal Operating mode(1) PortsP20P21P22P23P24P25P26P27P30P31P32P33P34-P37P60-P63P64Note 2P65No

26µPD78214 Sub-Series(2) Pins other than those which function as portsTO0-TO3CIRxDTxDASCKSB0SISOSCKNMIINTP0INTP1INTP2INTP3INTP4INTP5AD0-AD7A8-A15A16-A

27Chapter 2 Pin Functions22.1.2 PROM Programming Mode (only for the µPD78P214, P20/NMI = 12.5 V, RESET = L)PinP20/NMIRESETA0-A14D0-D7CEOEVPPVDDVSSN

28µPD78214 Sub-Series(a) When functioning as a portSignals applied to these pins can be read and these pins can be tested, regardless of whether these

29Chapter 2 Pin Functions2Table 2-2 Port 3 Operating Mode (n = 0 to 7)P30P31P32P33P34P35P36P37RxD inputTxD outputSCK input/outputSO output/SB0 inpu

30µPD78214 Sub-Series(6) P60 to P67 (port 6): Output (P60 to P63) and tristate inputs/outputs (P64 to P67)Port 6 is an eight-bit I/O port with output

PREFACEUsers:This manual is aimed at engineers who need to be familiar with the capabilities of the µPD78214 sub-series forapplication program develo

31Chapter 2 Pin Functions2(8) ASTB (address strobe): OutputTiming signal output used for latching addresses externally to enable access to external

32µPD78214 Sub-Series(9) VSSGround.(10) NC (non-connection)Not connected inside the chip.

33Chapter 2 Pin Functions22.3 I/O CIRCUITS AND UNUSED-PIN HANDLINGTable 2-4 lists the types of I/O circuits provided for each pin and describes how

34µPD78214 Sub-SeriesFig. 2-1 I/O Circuits Provided for PinsType 1INVDDPNType 2INSchmitt trigger input with hysteresis characteristicsType 4DataVDDPN

35Chapter 2 Pin Functions22.4 NOTES(1) While the RESET signal is being applied, pins P60 to P63 are high impedance. When the RESET signal isreleas

36

373CHAPTER 3 CPU FUNCTION3.1 MEMORY SPACEThe µPD78214 can access a memory space of up to 1M byte. Figs. 3-1 to 3-4 show the corresponding memorymap

38µPD78214 Sub-SeriesFig. 3-1 Memory Map of µPD78212 (EA Pin Driven High)Notes 1. Accessed in 1M-byte expansion mode.2. External SFR areaRemark The s

39Chapter 3 CPU Function3Fig. 3-2 Memory Map of µPD78212 (EA Pin Driven Low)Notes 1. Accessed in 1M-byte expansion mode.2. External SFR areaRemark

40µPD78214 Sub-SeriesFig. 3-3 Memory Map of µPD78213, µPD78214, or µPD78P214 (EA Pin Driven Low)Notes 1. Accessed in 1M-byte expansion mode.2. Extern

PD78P214PD78P214(A)µµPD78214PD78214(A)µµPD78213PD78213(A)µµPD78212PD78212(A)µµPROM 16KRAM 512ROM 16KRAM 512ROM-lessRAM 512ROM 8KRAM 384To check

41Chapter 3 CPU Function3Fig. 3-4 Memory Map of µPD78214, µPD78P214 (EA Pin Driven High)Notes 1. Accessed in 1M-byte expansion mode.2. Accessed in

42µPD78214 Sub-Series3.1.1 Internal Program Memory AreaIn the area from 00000H to 03FFFH (00000H to 01FFFH for the µPD78212), a 16K × 8 bit ROM (8K ×

43Chapter 3 CPU Function33.1.2 Internal RAM AreaA 512-byte (384-byte for the µPD78212) general-purpose static RAM is incorporated into the area fro

44µPD78214 Sub-SeriesTo access the space, specify the bank to be used (high-order four bits of address, A16 to A19) in the bank register(P60 to P63 of

45Chapter 3 CPU Function33.2 REGISTERS3.2.1 Program Counter (PC)This 16-bit binary counter holds the address of the program to be executed next (s

46µPD78214 Sub-Series(3) Register bank selection flags (RBS0, RBS1)These two flags are used to select one of four register banks (see Table 3-2).The f

47Chapter 3 CPU Function3Fig. 3-9 Data Saved to the Stack AreaFig. 3-10 Data Restored from the Stack AreaPUSH rp instructionStackRegister pair, lo

48µPD78214 Sub-SeriesFig. 3-11 Configuration of General-Purpose RegistersA E1HB E3HD E5HH E7HA E9HB EBHD EDHH EFHA F1HB F3HD F5HH F7HA F9HB FBHD FDHH

49Chapter 3 CPU Function3(2) FunctionGeneral-purpose registers can be operated in units of eight bits. They can also be operated in units of 16 bit

50µPD78214 Sub-Series3.2.5 Special Function Registers (SFR)A mode register, control register, and other registers with special functions, which are b

Never use the code combinations indicated "Not to be set" in the register descriptions.Characters likely to be confused: 0 (zero) and O (upp

51Chapter 3 CPU Function30FF00H0FF02H0FF03H0FF04H0FF05H0FF06H0FF07H0FF0AH0FF0BH0FF0CH0FF10H0FF11H0FF12H0FF13H0FF14H0FF15H0FF16H0FF17H0FF18H0FF19H0FF

52µPD78214 Sub-Series0FF50H0FF51H0FF52H0FF54H0FF56H0FF5CH0FF5DH0FF5EH0FF5FH0FF68H0FF6AH0FF80H0FF82H0FF86H0FF88H0FF8AH0FF8CH0FF8EH0FF90H0FFC0H0FFC4H0FF

53Chapter 3 CPU Function33.3 NOTES(1) A program fetch from the internal RAM area is prohibited.(2) Operation of the stack pointerIn stack addressin

54

554CHAPTER 4 CLOCK GENERATOR4.1 CONFIGURATION AND FUNCTIONA clock generator generates and controls the internal system clock (CLK) sent to the CPU.

56µPD78214 Sub-SeriesRemark Different uses of the crystal and ceramic resonatorGenerally, a crystal’s oscillation frequency is quite stable. Crystals

57Chapter 4 Clock Generator4Fig. 4-4 Notes on Connection of the OscillatorX2PD78214µX1 VSSCautions 1. Place the oscillator as close as possible to

58µPD78214 Sub-Series(c) A varying high current flows too close to the signalline.(d)A current flows through the ground line of theoscillator. (The p

595CHAPTER 5 PORT FUNCTIONS5.1 DIGITAL I/O PORTSThe µPD78214 has the ports shown in Fig. 5-1. These ports can be used for various types of control.

60µPD78214 Sub-SeriesTable 5-1 Port FunctionsPort 0Port 2Port 3Port 4NotePort 5NotePort 6NotePort 7Software-specified pull-up resistorName Pin nameP0

• Documents related to development toolsIE-78210-R In-Circuit Emulator SystemSoftware Operator's ManualCC78K Series C Compiler User's Manual

61Chapter 5 Port Functions55.2.1 Hardware ConfigurationFig. 5-2 shows the hardware configuration of port 0.Fig. 5-2 Configuration of Port 05.2.2

62µPD78214 Sub-Series5.2.3 OperationPort 0 is an output-only port.Once port 0 is put in the output mode, the output latch becomes operable, enabling

63Chapter 5 Port Functions55.3 PORT 2Port 2 is an 8-bit input-only port. P22 through P27 have a software-programmable built-in pull-up resistor.

64µPD78214 Sub-Series5.3.1 Hardware ConfigurationFig. 5-6 shows the configuration of port 2Fig. 5-6 Block Diagram of Port 2Note P20 or P21 does not

65Chapter 5 Port Functions5Fig. 5-7 Port Specified as an Input PortCaution For the in-circuit emulator, the level of each port 2 pin from which noi

66µPD78214 Sub-SeriesFig. 5-9 Connection of Pull-Up Resistors (Port 2)Caution P22 through P26 are not pulled up immediately after a reset. In this c

67Chapter 5 Port Functions5Table 5-4 Port 3 Operating Modes (n = 0 through 7)ConditionP30P31P32P33P34P35P36P37Mode Control signal I/O modePMC3n = 1

68µPD78214 Sub-Series5.4.1 Hardware ConfigurationFig. 5-10 through 5-13 show the configuration of port 3.Fig. 5-10 Block Diagram of P30 (Port 3)P30I

69Chapter 5 Port Functions5Fig. 5-11 Block Diagram of P31, and P34 through P37 (Port 3)Internal busRDPUOWRPUOWRPM3nPort 3 mode registerPM3nWRPMC3nP

70µPD78214 Sub-SeriesFig. 5-12 Block Diagram of P32 (Port 3)★Internal busRDP32P32RDPUOWRPUOPull-up resistor option registerPUO3WRPM32Port 3 mode regi