NEC PD75P402 User Manual Page 157
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CHAPTER 8. RESET FUNCTION
CHAPTER 8. RESET FUNCTION
When low level is input to the RESET pin, system reset is applied and the hardware enters the state shown in
Table 8-1.
When the RESET input goes from low level to high level, the reset state is released. Then, the contents of the
lower-order three bits of address 000H of the reset vector table are set into program counter (PC) bits 10 to 8 and
the contents of the low-order three bits of address 001H are set into PC bits 7 to 0 and the program branches and
begins executing from that branch address. Therefore, reset and starting from an arbitrary address is possible.
Initialize the contents of each register as required in the program.
The RESET pin is a Schmitt-triggered input with hysteresis characteristics at the threshold level. To prevent
misoperation by noise, a function which rejects narrow band noise by analog delay is also provided on the chip
(see Fig. 8-1).
For reset operation at power-on, provide an ample oscillation stabilization time from power-on to reset signal
acceptance as shown in Fig. 8-2.
Fig. 8-1 Reset Signal Acceptance
RESET
Analog
Delay
Analog
Delay
Analog
Delay
Rejected
as Noise
Reset
Acceptance
Reset
Release
Contents of reset
vector table set
in PC (PC initialize)
Reset branch destination
address instruction
execution
Fig. 8-2 Reset at Power-on
RESET
Reset branch
destination address
instruction execution
Analog
Delay
Oscillation
Stabilization
Time
Reset
Release
V
DD
Contents of reset
vector table set
in PC (PC initialize)
- PD75402A 1
- CONTENTS 6
- CONTENTS OF FIGURES 9
- Fig. No Title Page 9
- Fig. No. Title Page 10
- Table No. Title Page 11
- CHAPTER 1. GENERAL 12
- 1.1 OUTLINE OF FUNCTIONS 13
- 1.4 BLOCK DIAGRAM 16
- Remarks Parentheses for the 16
- PD75P402 16
- DD : Power supply 17
- SS : Ground 17
- PD75P402C/CT 18
- PD75402AGB-×××-3B4 19
- PD75P402GB-×××-3B4 19
- (2) PROM mode 20
- CHAPTER 2. PIN FUNCTIONS 21
- P00 P10 INT0 24
- P01 SCK P12 INT2 24
- P02 SO/SB0 24
- Address 76543210 Symbol 48
- Internal Bus 54
- Remarks n = 0 to 3 55
- Output Latch 56
- Φ Φ Φ Φ 63
- 2-Machine Cycles 64
- Manipulation Instruction 64
- Instruction 64
- Execution 64
- Input Timing 64
- Selector 65
- XX/4 (PCC1, PCC0 67
- External 68
- XX = 4.19 MHz) 71
- XX = 4.19 MHz 75
- PCL Pin 76
- XX (31.3 ms) 78
- XX (19.5 ms) 78
- ➁ Clear CSIE 88
- • • • 104
- 1 2 3 4 5 6 7 8 109
- SB0 ACK BUSY READY 111
- XX = 4.19 MHz operation 112
- Fig. 5-44 ACKT Operation 118
- “H”SCK 121
- 1 2 7 8 9 10 122
- Genera- 127
- ➀ READ command 132
- ➂ STATUS command 134
- ➄ CHGMST command 135
- SMP = tCY or 64/fXX 142
- X/64 is selected as 143
- 6.4 INTERRUPT SEQUENCE 145
- A B C D 146
- Interrupt 146
- (INTxxx) 146
- A C D 147
- Instruction other 147
- CHAPTER 8. RESET FUNCTION 157
- CHAPTER 9. INSTRUCTION SET 159
- ∧ (HL) *1 164
- ∨ (HL) *1 164
- ∧ (f mem. bit) *3 165
- ∨ (f mem. bit) *3 165
- Note 1. Instruction Group 166
- 2. I/O instructions 166
- 1 R0 reg 167
- 1 reg-pair 167
- 2N1N0 IE××× 167
- MOV A, #n4 170
- MOV rp, #n8 170
- MOV A, @HL 170
- MOV @HL, A 171
- MOV A, mem 171
- MOV XA, mem 171
- MOV mem, A 171
- MOV mem, XA 171
- XCH A, @HL 172
- XCH A, mem 172
- XCH XA, mem 172
- XCH A, reg1 172
- MOVT XA, @PCXA 173
- ADDS A, #n4 174
- ADDS A, @HL 174
- ADDC A, @HL 174
- AND A, @HL 174
- OR A, @HL 175
- XOR A, @HL 175
- INCS reg 177
- INCS mem 177
- DECS reg 177
- SKE reg, #n4 178
- SKE A, @HL 178
- ∧ (bit specified by operand) 181
- ∨ (bit specified by operand) 181
- BR $addr 182
- BRCB !caddr 182
- CALLF !faddr 183
- EI IEXXX 185
- DI IEXXX 185
- IN A, PORTn 186
- OUT PORTn, A 186
- 2. EV-9200G-44 192
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