Nec PD750008 User Manual

µPD7500084 BIT SINGLE-CHIP MICROCOMPUTER©1995USER'S MANUALµPD750004µPD750006µPD750008µPD75P0016Document No. U10740EJ2V0UM00 (2nd edition)(Previou

- ii -CHAPTER 3 FEATURES OF THE ARCHITECTURE AND MEMORY MAP ... 213.1 DATA MEMORY BANK STRUCTURE AND ADDRESSING

80µPD750008 USER'S MANUALTable 5-3. Operations by I/O Port Manipulation InstructionsInstructionPort and pin operationInput mode Output modeSKT &

81CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS5.1.5 Specification of Bilt-in Pull-Up ResistorsA pull-up resistor can be contained at each port pin of th

82µPD750008 USER'S MANUALFigure 5-8. Pull-Up Resistor Specification Register FormatPull-up resistor specification register group APull-up resist

83CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONSFigure 5-9. I/O Timing Chart of Digital I/O Ports (2/2)(b) When data is input by a 2-machine cycle instruc

84µPD750008 USER'S MANUAL5.2 CLOCK GENERATORThe clock generator supplies various clock signals to the CPU and peripheral hardware to control th

85CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS5.2.2 Functions and Operations of the Clock GeneratorThe clock generator generates the following clocks, a

86µPD750008 USER'S MANUAL(1) Processor clock control register (PCC)The PCC is a 4-bit register for selecting a CPU clock F with the low-order two

87CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONSFigure 5-12. Format of the Processor Clock Control RegisterAddressFB3H3210PCC3 PCC2 PCC1 PCC0SymbolPCCCPU c

88µPD750008 USER'S MANUAL(2) System clock control register (SCC)The SCC is a 4-bit register for selecting CPU clock F with the least significant

89CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS(3) System clock oscillatorThe main system clock oscillator operates with a crystal resonator or ceramic res

- iii -5.3.5 Operation of the Watchdog Timer ... 1025.3.6 Other Functions ...

90µPD750008 USER'S MANUALAny line carrying a high pulsating current must be kept away as far as possible.• The grounding point of the capacitor o

91CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONSFigure 5-16. Examples of Oscillator Connections Which Should Be Avoided (2/2)(c) A high pulsating current i

92µPD750008 USER'S MANUAL(4) Frequency dividerThe frequency divider divides the output (fX) of the main system clock oscillator to generate vario

93CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS(6) Sub-oscillator control register (SOS)The SOS register specifies whether to use the built-in feedback reg

94µPD750008 USER'S MANUAL5.2.3 System Clock and CPU Clock Setting(1) Time required to change the system clock and CPU clockThe system clock and

95CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS(2) Procedure for changing the system clock and CPU clockThe procedure for changing the system clock and CPU

96µPD750008 USER'S MANUAL5.2.4 Clock Output Circuit(1) Configuration of the clock output circuitFigure 5-20 shows the configuration of the cloc

97CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS(3) Clock output mode register (CLOM)The CLOM is a 4-bit register to control clock output.The CLOM is set by

98µPD750008 USER'S MANUAL(4) Application to remote control outputThe clock output function of the µPD750008 is applicable to remote control outpu

99CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS5.3 BASIC INTERVAL TIMER/WATCHDOG TIMERThe µPD750008 contains an 8-bit basic interval timer/watchdog timer

- iv -CHAPTER 8 RESET FUNCTION ... 225CHAPTE

100µPD750008 USER'S MANUALWhen bit 3 is set to 1, the BT is cleared, and the basic interval ltimer/watchdog timer interrupt request flag(IRQBT) i

101CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS5.3.3 Watchdog Timer Enable Flag (WDTM)WDTM, when set, is a flag for enabling the generation of the reset

102µPD750008 USER'S MANUAL5.3.5 Operation of the Watchdog TimerWhen WDTM is set to 1, the basic interval timer/watchdog timer functions as a wa

103CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS······Module 1:SET1SELSET1MBEMB15BTM.3Processing completes within 5.46 ms.······Module 2:SET1SELSET1

104µPD750008 USER'S MANUAL(2) Reading the countThe count status of the basic interval timer (BT) can be read by using an 8-bit manipulation instr

105CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONSMOV XA, BCMOV BUFF, XA ; Store dataSET1 FLAG ; Set data presence flagRETI5.4 CLOCK TIMERThe µPD750008 con

106µPD750008 USER'S MANUAL5.4.1 Configuration of the Clock TimerFigure 5-26 shows the configuration of the clock timer.Figure 5-26. Block Diag

107CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONSExample Time is set using the main system clock (4.19 MHz), and buzzer output is enabled:CLR1 MBEMOV XA, #8

108µPD750008 USER'S MANUAL5.5 TIMER/EVENT COUNTERThe µPD750008 has one timer/event counter channel (channel 0) and one timer counter channel (c

109CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONSFigure 5-28. Block Diagram of the Timer/Event Counter (Channel 0)Count register (8)TI0MPXTimer operation s

- v -APPENDIX A FUNCTIONS OF THE µPD75008, µPD750008, AND µPD75P0016 ... 299APPENDIX B DEVELOPMENT TOOLS ...

110µPD750008 USER'S MANUAL Figure 5-29. Block Diagram of the Timer Counter (Channel 1)Count register (8)MPXTimer operation start signal888From t

111CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS(1) Timer/event counter mode register (TM0, TM1)The mode register (TMn) is an 8-bit register which controls

112µPD750008 USER'S MANUALFigure 5-30. Timer/Event Counter Mode Register (Channel 0) FormatWhen fX = 4.19 MHzTM05000011TM06001111TM0

113CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONSFigure 5-31. Timer Counter Mode Register (Channel 1) FormatAddressFA8H76TM165TM154TM143TM132TM1210

114µPD750008 USER'S MANUAL(2) Timer/event counter output enable flag (TOE0, TOE1)The timer/event counter output enable flag (TOE0, TOE1) controls

115CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONSFigure 5-33. Timer/Event Counter Mode Register Setup (1/2)(a) In the case of timer/event counter (channel

116µPD750008 USER'S MANUALFigure 5-33. Timer/Event Counter Mode Register Setup (2/2)(b) In the case of timer counter (channel 1)(b) Timer/event

117CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS(2) Timer/event counter time setting[Timer setup time] (cycle) is found by dividing [modulo register conten

118µPD750008 USER'S MANUAL(3) Timer/event counter operationThe timer/event counter operates as follows.Figure 5-35 shows the configuration of the

119CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONSFigure 5-36. Count Operation Timing(4) Applications of the timer/event counter(a) Timer/event counter is u

- vi -LIST OF FIGURES (1/4)Figure No. Title Page2-1 Pin Input/Output Circuits ...

120µPD750008 USER'S MANUAL<Sample program>SEL MB15MOV XA,#100 – 1MOV TMOD0,XA ; Set the modulo registerMOV XA,#00001100BMOV TM0,XA ; Set th

121CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS(3) Error in reading the count registerThe contents of the count register can be read using an 8-bit data m

122µPD750008 USER'S MANUAL(5) Operation after the modulo register is changedThe contents of the modulo register are changed when an 8-bit data me

123CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS5.6 SERIAL INTERFACE5.6.1 Serial Interface FunctionsThe µPD750008 contains a clock synchronous 8-bit se

124µPD750008 USER'S MANUALFigure 5-38. Example of the SBI System Configuration5.6.2 Configuration of Serial InterfaceFigure 5-39 shows the blo

125CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONSFigure 5-39. Block Diagram of the Serial InterfaceInternal bus8888/4P03/SI0/SB1P02/SO0/SB0P01/SCK(8)fx/23f

126µPD750008 USER'S MANUAL(1) Serial operation mode register 0 (CSIM)CSIM is an 8-bit register which specifies a serial interface operation mode,

127CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS(9) Serial clock control circuitThe serial clock control circuit controls the serial clock to be supplied t

128µPD750008 USER'S MANUALFigure 5-40. Format of Serial Operation Mode Register (CSIM) (2/4)Serial interface operation enable/disable specifica

129CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONSFigure 5-40. Format of Serial Operation Mode Register (CSIM) (3/4)Serial interface operation mode selecti

- vii -LIST OF FIGURES (2/4)Figure No. Title Page5-9 I/O Timing Chart of Digital I/O Ports ...

130µPD750008 USER'S MANUALFigure 5-40. Format of Serial Operation Mode Register (CSIM) (4/4)Remarks 2. The P01/SCK pin assumes any of the follo

131CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS(2) Serial bus interface control register (SBIC)Figure 5-41 shows the format of the serial bus interface co

132µPD750008 USER'S MANUALFigure 5-41. Format of Serial Bus Interface Control Register (SBIC) (2/3)Busy enable bit (R/W)BSYE 0 <1> The bus

133CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS Figure 5-41. Format of Serial Bus Interface Control Register (SBIC) (3/3)Bus release detection flag (

134µPD750008 USER'S MANUAL(3) Shift register (SIO)Figure 5-42 shows the configuration of peripheral hardware of shift register. SIO is an 8-bit

135CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS(a) Slave address detection[In the SBI mode]SVA is used when the µPD750008 is connected as a slave device t

136µPD750008 USER'S MANUALNote The status of the P01/SCK pin is selectable.Remark (R): Read only(W): Write onlySerial interface operation enabl

137CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS5.6.5 Three-Wire Serial I/O Mode OperationsThe three-wire serial I/O mode is compatible with other modes

138µPD750008 USER'S MANUALSerial interface operation enable/disable specification bit (W)Shift register operation Serial clock counter IRQCSI fla

139CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS(b) Serial bus interface control register (SBIC)To use the three-wire serial I/O mode, set SBIC as shown be

- viii -LIST OF FIGURES (3/4)Figure No. Title Page5-45 Operations of RELT and CMDT ...

140µPD750008 USER'S MANUALSCKSIIRQCSI1SO23 4 5 6 78DI0DO0DI1DO1DI2DO2DI3DO3DI4DO4DI5DO5DI6DO6DI7DO7Transfer operation is started in phase with fa

141CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS(4) SignalsFigure 5-45 shows operations of RELT and CMDT.Figure 5-45. Operations of RELT and CMDT(5) Switc

142µPD750008 USER'S MANUAL(6) Transfer startSerial transfer is started by writing transfer data into shift register (SIO), provided that the foll

143CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS(b) Data is transmitted and received starting with the LSB on an external clock (slave operation).(In this

144µPD750008 USER'S MANUALSCKMaster CPU(µPD750008)SB0, SB1Slave CPUSCKSB0, SB1VDD2-wire serial I/O 2-wire serial I/O<Sample program> (mast

145CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS(a) Serial operation mode register (CSIM)To use the two-wire serial I/O mode, set CSIM as shown below. (Fo

146µPD750008 USER'S MANUALSerial interface operation mode selection bit (W)CSIM4 CSIM3 CSIM2 Shift register sequence SO pin function SI pin funct

147CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONSBus release trigger bit (W)RELT Control bit for bus release signal (REL) trigger output.By setting RELT = 1

148µPD750008 USER'S MANUAL(3) Serial clock selectionTo select the serial clock, manipulate bits 0 and 1 of serial operation mode register (CSIM).

149CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS(6) Error detectionIn the two-wire serial I/O mode, the state of serial bus SB0 or SB1 being used for commu

- ix -LIST OF FIGURES (4/4)Figure No. Title Page5-81 Format of the Bit Sequential Buffer ...

150µPD750008 USER'S MANUALThe µPD750008, which is the master microcomputer, outputs a serial clock, and all slave microcomputersoperate with an e

151CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONSCautions 1. In the SBI mode, the serial data bus pin SB0 (or SB1) is an open-drain output. Sothe serial da

152µPD750008 USER'S MANUAL(2) SBI definitionThe format of serial data and signal used in the SBI mode are described below.Serial data to be trans

153CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS(a) Bus release signal (REL)When the SCK line is high (the serial clock is not output), the SB0 (or SB1) li

154µPD750008 USER'S MANUALFigure 5-55. Slave Selection Using an Address(d) Command and dataThe master sends commands to the slave selected by se

155CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONSFigure 5-58. Acknowledge Signal[When output in phase with the 11th clock of SCK][When output in phase with

156µPD750008 USER'S MANUALSB0, SB189ACKBUSY READYSCK(f) Busy signal (BUSY) and ready signal (READY)The busy signal informs the master that a slav

157CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONSSerial interface operation enable/disable specification bit (W)Shift register operation Serial clock counte

158µPD750008 USER'S MANUALSerial clock selection bit (W)CSIM1 CSIM0 Serial clock SCK pin mode0 0 External clock applied to SCK pin Input0 1 Timer

159CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONSAcknowledge detection flag (R)ACKD Condition for being cleared (ACKD = 0) Condition for being set (ACKD = 1

- x -LIST OF TABLES (1/2)Table No. Title Page1-1 Features of the Products ...

160µPD750008 USER'S MANUALBus release trigger bit (W)RELT Control bit for bus release signal (REL) trigger output.By setting RELT = 1, the SO lat

161CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONSFigure 5-60. Operations of RELT, CMDT, RELD, and CMDD (Master)Figure 5-61. Operations of RELT, CMDT, RELD

162µPD750008 USER'S MANUALFigure 5-62. Operation of ACKTCaution Do not set the ACKT until the transfer is completed.Figure 5-63. Operation of A

163CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONSSIOSCK98D2 D1 D0 SB0, SB1ACKD76ACKTransfer start requestTransfer startFigure 5-63. Operation of ACKE (2/2)

164µPD750008 USER'S MANUALFigure 5-64. Operation of ACKD (2/2)(c) Clear timing for case where start of transfer is directed during BUSYFigure 5

165CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONSTable 5-10. Various Signals Used in the SBI Mode (1/2)SCKSB0, SB1“H”“H”SCKSB0, SB1Rising edge of SB0 or S

166µPD750008 USER'S MANUALTable 5-10. Various Signals Used in the SBI Mode (2/2)Synchronous clock for outputting address/command/data, ACK si

167CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS(6) Pin configurationThe configurations of serial clock pin SCK and serial data bus pin (SB0 or SB1) are as

168µPD750008 USER'S MANUAL(7) Address match detection methodIn the SBI mode, communication starts when the master selects a particular slave devi

169CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONSFigure 5-67. Address Transfer Operation from Master Device to Slave Device (WUP = 1)Program processingHard

- xi -LIST OF TABLES (2/2)Table No. Title Page7-1 Operation Statuses in the Standby Mode ...

170µPD750008 USER'S MANUALFigure 5-68. Command Transfer Operation from Master Device to Slave DeviceProgram processingHardware operationProgram

171CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONSFigure 5-69. Data Transfer Operation from Master Device to Slave DeviceProgram processingHardware operatio

172µPD750008 USER'S MANUALFigure 5-70. Data Transfer Operation from Slave Device to Master DeviceProgram processingHardware operationProgram pro

173CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS(10) Transfer startSerial transfer is started by writing transfer data in shift register (SIO), provided th

174µPD750008 USER'S MANUAL(12) SBI modeThis section describes an example of application which performs serial data communication in the SBImode.

175CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS(b) Explanation of commands(i) Types of commandsThis example uses the following commands:<1> READ com

176µPD750008 USER'S MANUALWhen the slave receives a transmission data count, if it has data enough for transmitting thespecified number of bytes

177CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS<3> STATUS commandThe STATUS command reads the status of the current slave.Figure 5-75. Transfer For

178µPD750008 USER'S MANUAL<4> RESET commandThe RESET command changes the currently selected slave to a non-selected slave. Whena RESET com

179CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONSIf ACK is not returned from the slave within a predetermined period after transmissioncompletion, the occur

12345678910GENERALFEATURES OF THE ARCHITECTURE AND MEMORY MAPMASK OPTIONRESET FUNCTIONINTERRUPT AND TEST FUNCTIONSPERIPHERAL HARDWARE FUNCTIONSINTERNA

- xii -[MEMO]

180µPD750008 USER'S MANUALP01/SCKP01 output latchSCKTo internal circuitAddress FF0H.1SCK pin output modeFrom the serial clock control circuit

181CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS5.7 BIT SEQUENTIAL BUFFER: 16-BITThe bit sequential buffer (BSB) is special data memory for bit manipula

182µPD750008 USER'S MANUALExample To output 16-bit data of BUFF1 and BUFF2 serially from bit 0 of port 3:CLR1 MBEMOV XA,BUFF1MOV BSB0,XA ; Set BS

183CHAPTER 6 INTERRUPT AND TEST FUNCTIONSCHAPTER 6 INTERRUPT AND TEST FUNCTIONSThe µPD750008 has seven vectored interrupt sources and two test input

184µPD750008 USER'S MANUALFigure 6-1. Block Diagram of Interrupt Control Circuit*2IM214IRQBTIRQ4IRQ0IRQ1IRQCSIIRQT0IRQT1IRQWIRQ2INTBTINT

185CHAPTER 6 INTERRUPT AND TEST FUNCTIONS6.2 TYPES OF INTERRUPT SOURCES AND VECTOR TABLESTable 6-1 lists the types of interrupt sources, and Figure

186µPD750008 USER'S MANUALThe column of interrupt priority in Table 6-1 indicates a priority assigned when multiple interrupt requestsoccur concu

187CHAPTER 6 INTERRUPT AND TEST FUNCTIONS6.3 VARIOUS DEVICES TO CONTROL INTERRUPT FUNCTIONS(1) Interrupt request flags and interrupt enable flagsTh

188µPD750008 USER'S MANUALTable 6-2. Set Signals for Interrupt Request FlagsInterruptSet signals for interrupt request flagsInterruptrequest fla

189CHAPTER 6 INTERRUPT AND TEST FUNCTIONSFigure 6-3. Interrupt Priority Specification RegisterIPS0IPS1IPS2IPS30123IPSSymbolFB2HAddress00000101001110

1CHAPTER 1 GENERALCHAPTER 1 GENERALThe µPD750004, µPD750006, µPD750008, and µPD75P0016 are 75XL series 4-bit single-chip microcom-puters. The 75XL

190µPD750008 USER'S MANUAL(3) Configurations of the INT0, INT1, and INT4 circuits(a) As shown in Figure 6-4 (a), the INT0 circuit accepts an exte

191CHAPTER 6 INTERRUPT AND TEST FUNCTIONSFigure 6-4. Configurations of the INT0, INT1, and INT4 Circuits(a) Configuration of the INT0 circuit(b) C

192µPD750008 USER'S MANUALFigure 6-5. I/O Timing of a Noise EliminatorRemark tSMP = tCY or 64/fXINT0Shaped outputINT0INT0INT0Shaped outputShaped

193CHAPTER 6 INTERRUPT AND TEST FUNCTIONSFigure 6-6. Format of Edge Detection Mode Registers(a) INT0 edge detection mode register (IM0)(b) INT1 ed

194µPD750008 USER'S MANUAL(4) Interrupt status flagsThe interrupt status flags (IST0 and IST1), which are contained in the PSW, indicate the stat

195CHAPTER 6 INTERRUPT AND TEST FUNCTIONS6.4 INTERRUPT SEQUENCEWhen an interrupt occurs, it is processed using the procedure shown in Figure 6-7.Fi

196µPD750008 USER'S MANUAL6.5 MULTIPLE INTERRUPT PROCESSING CONTROLThe µPD750008 can handle multiple interrupts by either of the following meth

197CHAPTER 6 INTERRUPT AND TEST FUNCTIONS(2) Multiple interrupt processing by changing the interrupt status flagsChanging the interrupt status flags

198µPD750008 USER'S MANUAL6.6 PROCESSING OF INTERRUPTS SHARING A VECTOR ADDRESSInterrupt sources INTBT and INT4 share a vector table, so an int

199CHAPTER 6 INTERRUPT AND TEST FUNCTIONSExamples 1. To use both INTBT and INT4 as having the higher priority and give priority to INT4DISKTCLR IRQ4

2µPD750008 USER'S MANUAL1.1 FUNCTION OVERVIEWItem FunctionInstruction execution •0.95, 1.91, 3.81, 15.3 µs (when the main system clock operates a

200µPD750008 USER'S MANUAL6.7 MACHINE CYCLES FOR STARTING INTERRUPT PROCESSINGWith the µPD750008 series, the following machine cycles are used

201CHAPTER 6 INTERRUPT AND TEST FUNCTIONS(2) When IRQn is set during an instruction other than that described in (1)(a) When IRQn is set at the last

202µPD750008 USER'S MANUAL6.8 EFFECTIVE USE OF INTERRUPTSThe interrupt function can be used more effectively in the ways described below.(1) MB

203CHAPTER 6 INTERRUPT AND TEST FUNCTIONS(1) Interrupt enable/disable<1> A RESET signal disables all interrupts.<2> Interrupt enable flag

204µPD750008 USER'S MANUAL(2) Example of using INTBT, INT0 (falling edge active), and INTT0 without multiple interrupt processing<1> A RESE

205CHAPTER 6 INTERRUPT AND TEST FUNCTIONS(3) Nesting of interrupts with higher priority (INTBT has higher priority and INTT0 and INTCSI havelower pri

206µPD750008 USER'S MANUAL(4) Execution of held interrupts (interrupt requests when interrupts are disabled)<1> If INT0 is set when interru

207CHAPTER 6 INTERRUPT AND TEST FUNCTIONS(5) Execution of held interrupts – two interrupts with lower priority occur concurrently –<1> When INT

208µPD750008 USER'S MANUAL(6) Executing pending interrupt – interrupt occurs during interrupt processing (INTBT has higherpriority and INTT0 and

209CHAPTER 6 INTERRUPT AND TEST FUNCTIONS(7) Enabling of level-two interrupts (enabling level-two INTT0 and INT0 interrupts with INTCSI and INT4handl

3CHAPTER 1 GENERAL1.2 ORDERING INFORMATIONPart number Package On-chip ROMµPD750004CU-xxx 42-pin plastic shrink DIP (600 mil) Masked ROMµPD750004GB-xx

210µPD750008 USER'S MANUAL6.10 TEST FUNCTION6.10.1 Test SourcesThe µPD750008 has two test sources. INT2 provides two types of edge-detection

211CHAPTER 6 INTERRUPT AND TEST FUNCTIONS(2) INT2 and key interrupt (KR0 to KR7) hardwareFigure 6-10 shows the configuration of INT2 and KR0 to KR7.T

212µPD750008 USER'S MANUALFigure 6-10. Block Diagram of the INT2 and KR0 to KR7 CircuitsINT2/P12KR7/P73KR6/P72KR5/P71KR4/P70KR3/P63KR2/P62KR1/P6

213CHAPTER 6 INTERRUPT AND TEST FUNCTIONSFigure 6-11. Format of INT2 Edge Detection Mode Register (IM2)Cautions 1. When the edge detection mode regi

214µPD750008 USER'S MANUAL[MEMO]

215CHAPTER 7 STANDBY FUNCTIONCHAPTER 7 STANDBY FUNCTIONThe µPD750008 provides a standby function to reduce the power consumption by the system. The

216µPD750008 USER'S MANUAL7.1 SETTING OF STANDBY MODES AND OPERATION STATUSTable 7-1. Operation Statuses in the Standby ModeNotes 1. Operation

217CHAPTER 7 STANDBY FUNCTIONCaution 2. Reset all the interrupt request flags before setting the standby mode. If an interruptsource whose interrupt

218µPD750008 USER'S MANUALFigure 7-1. Standby Mode Release Operation (2/2)(c) Release of the HALT mode by RESET signal(d) Release of the HALT

219CHAPTER 7 STANDBY FUNCTIONTable 7-2. Selection of a Wait Time with BTMNote This time does not include the time from the release of the STOP mode

4µPD750008 USER'S MANUAL1.3 DIFFERENCES AMONG SUBSERIES PRODUCTSItem µPD750004 µPD750006 µPD750008 µPD75P0016Program counter 12 bits 13 bits 14 b

220µPD750008 USER'S MANUAL7.4 SELECTION OF A MASK OPTIONFor the standby function of the µPD750008, either of the following two values can be se

221CHAPTER 7 STANDBY FUNCTIONINT4INT431.3 ms 31.3 msWaitLow-speedoperationSTOP modeOperating modeSTOP instructionVDD0 VP00/INT4CPU operationVoltage

222µPD750008 USER'S MANUAL(2) Application of the HALT mode (at fX = 4.19 MHz)<Intermittent operation under the following conditions>• The m

223CHAPTER 7 STANDBY FUNCTION<Sample program>(Initialization)MOV A,#0011BMOV PCC,A ; High-speed modeMOV XA,#05MOV WM,XA ; Subsystem clockEI IE4

224µPD750008 USER'S MANUAL[MEMO]

225CHAPTER 8 RESET FUNCTIONCHAPTER 8 RESET FUNCTIONThe µPD750008 is reset with the external reset signal (RESET) or the reset signal received from

226µPD750008 USER'S MANUALTable 8-1. Status of the Hardware after a Reset (1/2)Note Data of address 0F8H to 0FDH of the data memory becomes unde

227CHAPTER 8 RESET FUNCTIONTable 8-1. Statuses of the Hardware after a Reset (2/2)Processor clock control register(PCC)System clock control register

228µPD750008 USER'S MANUAL[MEMO]

229CHAPTER 9 WRITING TO AND VERIFYING PROGRAM MEMORY (PROM)CHAPTER 9 WRITING TO AND VERIFYING PROGRAM MEMORY (PROM)The program memory in the µPD75P0

5CHAPTER 1 GENERAL1.4 BLOCK DIAGRAMNotes 1. The program counter for the µPD750004 consists of 12 bits, 13 bits for the µPD750006 andµPD750008, and

230µPD75008 USER'S MANUAL9.1 OPERATING MODES WHEN WRITING TO AND VERIFYING THE PROGRAM MEMORYIf +6 V is applied to the VDD pin and +12.5 V is a

231CHAPTER 9 WRITING TO AND VERIFYING PROGRAM MEMORY (PROM)The timing for steps (2) to (12) is shown below.VPPVDDVPPVDD +1VDDVDDX1P40-P43P50-P53MD0

232µPD75008 USER'S MANUAL9.3 READING THE PROGRAM MEMORYThe procedure for reading the contents of program memory is described below. The read i

233CHAPTER 9 WRITING TO AND VERIFYING PROGRAM MEMORY (PROM)9.4 SCREENING OF ONE-TIME PROMBecause of its structure, it is difficult for NEC to compl

234µPD75008 USER'S MANUAL[MEMO]

235CHAPTER 10 MASK OPTIONCHAPTER 10 MASK OPTION10.1 PINThe pins of the µPD750008 have the following mask options:Table 10-1. Selecting Mask Optio

236µPD750008 USER'S MANUAL10.3 MASK OPTION FOR FEEDBACK RESISTOR OF SUBSYSTEM CLOCKFor the subsystem clock of the µPD750008, whether to enable

237CHAPTER 11 INSTRUCTION SETCHAPTER 11 INSTRUCTION SETThe instruction set of the µPD750008 is an improved and extended version of the 75X series in

238µPD750008 USER'S MANUAL11.1.2 Bit Manipulation InstructionsWith the µPD750008, a variety of instructions are available for bit manipulation.

239CHAPTER 11 INSTRUCTION SET11.1.4 Number System Conversion InstructionsAn application may need to convert the result of a 4-bit data addition or

6µPD750008 USER'S MANUAL1.5 PIN CONFIGURATION (TOP VIEW)(1) 42-pin plastic shrink DIP (600 mil)µPD750004CU-XXXµPD750006CU-XXXµPD750008CU-XXXµPD75

240µPD750008 USER'S MANUAL11.1.5 Skip Instructions and the Number of Machine Cycles Required for a SkipThe instruction set of the µPD750008 is

241CHAPTER 11 INSTRUCTION SET11.2 INSTRUCTION SET AND OPERATION(1) Operand identifier and descriptionThe operand field of an instruction must conta

242µPD750008 USER'S MANUAL(2) LegendA: A register; 4-bit accumulatorB: B registerC: C registerD: D registerE: E registerH: H registerL: L registe

243CHAPTER 11 INSTRUCTION SET(3) Explanation of symbols used for the addressing area columnRemarks 1. MB represents an accessible memory bank.2. For

244µPD750008 USER'S MANUAL(4) Explanation of the machine cycle columnS represents the number of machine cycles required when a skip instruction w

245CHAPTER 11 INSTRUCTION SETInMne-NumberMachineAddress-struc-monicOperation ofcycleOperation ing Skip conditiontion bytes areaMOV A,#n4 1 1 A <–

246µPD750008 USER'S MANUALIn-Mne-NumberMachineAddress-struc-monicOperandofcycleOperationingSkip conditiontionbytes areaMOVT XA,@PCDE 1 3 • µPD75

247CHAPTER 11 INSTRUCTION SETIn-Mne-NumberMachineAddress-struc-monicOperandofcycleOperationingSkip conditiontionbytes areaAND A,#n4 2 2 A <– A n4A

248µPD750008 USER'S MANUALInMne-NumberMachineAddress-struc-monicOperand ofcycleOperation ing Skip conditiontion bytes areaSET1 mem.bit 2 2 (mem.b

249CHAPTER 11 INSTRUCTION SETBranchInMne-NumberMachineAddress-struc-monicOperand ofcycleOperation ing Skip conditiontion bytes areaBR addr — — • µPD7

7CHAPTER 1 GENERAL(2) 44-pin plastic QFP (10 x 10 mm)µPD750004GB-XXX-3BS-MTXµPD750006GB-XXX-3BS-MTXµPD750008GB-XXX-3BS-MTXµPD75P0016GB-3BS-MTXNote Co

250µPD750008 USER'S MANUALBranchNote 1. Set register B to 0.2. Only the LSB is valid in register B.3. Only the low-order two bits are valid in re

251CHAPTER 11 INSTRUCTION SETInMne-NumberMachineAddress-struc-monicOperand ofcycleOperation ing Skip conditiontion bytes areaBR BCXA 2 3 • µPD750004*

252µPD750008 USER'S MANUALInMne-NumberMachineAddress-struc-monicOperand ofcycleOperation ing Skip conditiontion bytes areaCALLNote!addr 3 3 • µPD

253CHAPTER 11 INSTRUCTION SETInMne-NumberMachineAddress-struc-monicOperand ofcycleOperation ing Skip conditiontion bytes areaCALLFNote!faddr 2 3 • µP

254µPD750008 USER'S MANUALSubroutine stack controlInMne-NumberMachineAddress-struc-monicOperand ofcycleOperation ing Skip conditiontion bytes are

255CHAPTER 11 INSTRUCTION SETInMne-NumberMachineAddress-struc-monicOperand ofcycleOperation ing Skip conditiontion bytes areaRETINote 113• µPD7500040

256µPD750008 USER'S MANUALInMne-NumberMachineAddress-struc-monicOperand ofcycleOperation ing Skip conditiontion bytes areaSEL RBn 2 2 RBS <– n

257CHAPTER 11 INSTRUCTION SETSpecialInMne-NumberMachineAddress-struc-monicOperand ofcycleOperation ing Skip conditiontion bytes areaGETINotes1, 2tadd

258µPD750008 USER'S MANUAL11.3 INSTRUCTION CODES OF EACH INSTRUCTION(1) Explanations of the symbols for the instruction codesIn: Immediate data

259CHAPTER 11 INSTRUCTION SET(2) Bit manipulation addressing instruction codes*1 in the operand field indicates that there are three types of bit man

8µPD750008 USER'S MANUALPin nameP00-P03 : Port 0 RESET : Reset inputP10-P13 : Port 1 TI0 : Timer input 0P20-P23 : Port 2 PTO0, 1 : Programmable t

260µPD750008 USER'S MANUALInstructionMne-OperandInstruction codemonicB1B2B3Transfer MOV A,#n4 0111I3I2I1I0reg1,#n4 10011010 I3I2I1I01R2R1R0rp,#n8

261CHAPTER 11 INSTRUCTION SETInstructionMne-OperandInstruction codemonicB1B2B3Arithmetic/ADDS A,#n4 0110I3I2I1I0logicalXA,#n8 10111001 I7I6I5I4I3I2I1

262µPD750008 USER'S MANUALInstructionMne-OperandInstruction codemonicB1B2B3Increment/INCS reg 11000R2R1R0decrementrp1 10001P2P10@HL 10011001 0000

263CHAPTER 11 INSTRUCTION SETInstructionMne-OperandInstruction codemonicB1B2B3Branch BR !addr 10101011 00 addr$addr1 0000A3A2A1A0(+16) to (+2)(–1) to

264µPD750008 USER'S MANUAL11.4 FUNCTIONS AND APPLICATIONS OF THE INSTRUCTIONSThis section explains functions and applications of the instructio

265CHAPTER 11 INSTRUCTION SETMOV reg1,#n4Function: reg1 <– n4 n4 = I3-0: 0-FHTransfers the 4-bit immediate data n4 to A register reg1 (X, H,

266µPD750008 USER'S MANUALThen skips the immediately following instruction.When HL– (automatic decrement) is specified for the register pair, aut

267CHAPTER 11 INSTRUCTION SETMOV XA,memFunction: A <– (mem), X <– (mem+1) mem = D7-0: 00H-FEHTransfers the data at the data memory locati

268µPD750008 USER'S MANUALMOV reg1,AFunction: reg1 <– ATransfers the contents of the A register to register reg1 (X, H, L, D, E, B, C).MOV rp

269CHAPTER 11 INSTRUCTION SETXCH XA,@HLFunction: A <–> (HL), X <–> (HL+1)Exchanges the contents of the A register with the data at the d

9CHAPTER 2 PIN FUNCTIONSCHAPTER 2 PIN FUNCTIONS2.1 PIN FUNCTIONS OF THE µPD750008Table 2-1. Digital I/O Port Pins (1/2)Input/Also8 bit UponI/OPin

270µPD750008 USER'S MANUAL11.4.2 Table Reference InstructionsMOVT XA,@PCDEFunction: For the µPD750006 and µPD750008XA <– ROM (PC12-8+DE)Tra

271CHAPTER 11 INSTRUCTION SETFor example, if MOVT XA,@PCDE is located at a as shown above, the table data in page 3 specified bythe contents of the D

272µPD750008 USER'S MANUALMOVT XA,@BCXAFunction: For the µPD750006 and µPD750008XA <– (BCXA) ROMTransfers the low-order four bits of the table

273CHAPTER 11 INSTRUCTION SET11.4.3 Bit Transfer InstructionsMOV1 CY,fmem.bitMOV1 CY,pmem.@lMOV1 CY,@H+mem.bitFunction: CY <– (bit specified in

274µPD750008 USER'S MANUALADDS XA,#n8Function: XA <– XA+n8 ; Skip if carry. n8 = I7-0: 00H-FFHAdds the 8-bit immediate data n8 to the co

275CHAPTER 11 INSTRUCTION SETADDC XA,rp’Function: XA, CY <– XA+rp’+CYAdds the contents of register pair rp’ (XA, HL, DE, BC, XA’, HL’, DE’, BC’)

276µPD750008 USER'S MANUALSUBS rp’1,XAFunction: rp’1 <– rp’1+XA ; Skip if borrowSubtracts the contents of the XA register pair from the conte

277CHAPTER 11 INSTRUCTION SETAND A,@HLFunction: A <– A (HL)ANDs the contents of the A register with the data at the data memory location addresse

278µPD750008 USER'S MANUALOR rp’1,XAFunction: rp’1 <– rp’ XAORs the contents of register pair rp’1 (HL, DE, BC, XA’, HL’, DE’, BC’) with the

279CHAPTER 11 INSTRUCTION SET11.4.5 Accumulator Manipulation InstructionsRORC AFunction: CY <- A0, An-1 <- An, A3 <- CY (n = 1–3)Rotates

The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibitedwithout governmental license,

10µPD750008 USER'S MANUALTable 2-1. Digital I/O Port Pins (2/2)InputAlso8 bit UponI/OPinoutputused Function circuitasI/O resettypeNote 1P40- I/

280µPD750008 USER'S MANUALINCS memFunction: (mem) <– (mem)+1 ; Skip if (mem) = 0, mem = D7-0: 00H-FFHIncrements the data at the data memory

281CHAPTER 11 INSTRUCTION SETSKE XA,@HLFunction: Skip if A = (HL) and X = (HL+1)Skips the immediately following instruction if the contents of the A

282µPD750008 USER'S MANUALNOT1 CYFunction: CY <– CYInverts the carry flag. If it is 0, it is set to 1, or vice versa.11.4.9 Memory Bit Man

283CHAPTER 11 INSTRUCTION SETSkips the immediately following instruction if the bit specified by the 2-bit immediate data bit at the addressspecified

284µPD750008 USER'S MANUALAND1 CY, fmem.bitAND1 CY, pmem.@LAND1 CY, @H+mem.bitFunction: CY <– CY^(bit specified in operand)ANDs the content o

285CHAPTER 11 INSTRUCTION SETBR addr1Function: For the µPD750008 PC12-0 <–addr1addr1 = 0000H-1FFFHBranches to the address specified by the immed

286µPD750008 USER'S MANUALRemark "Function" in this section is applicable to the µPD750008 whose program counter consists of13 bits (ad

287CHAPTER 11 INSTRUCTION SETBR PCDEFunction: For the µPD750008 PC12-0 <– PC12-8 + DEPC7- 4 <– D, PC3-0 <– EBranches to the address specifie

288µPD750008 USER'S MANUALB C300D30E3011 8 7 4 3 012PCBR BCDEFunction: For the µPD750008 PC12-0 <– BCDEBranches to the address specified by

289CHAPTER 11 INSTRUCTION SET11.4.11 Subroutine Stack Control InstructionsCALLA !addr1Function: For the µPD750008(SP–2) <– x, x, MBE, RBE, (SP–3

11CHAPTER 2 PIN FUNCTIONSTable 2-2. Non-Port Pin FunctionsInput/AlsoUponI/OPinoutputused Functionresetcircuitas typeNote 1TI0 Input P13 Inputs exter

290µPD750008 USER'S MANUALCALLF !faddrFunction: For the µPD750008[Mk I mode](SP–1) <– PC7-4, (SP–2) <– PC3-0(SP–3) <– MBE, RBE, 0, PC12(

291CHAPTER 11 INSTRUCTION SETRETFunction: For the µPD750008[Mk I mode] PC11-8 <– (SP)MBE, RBE, 0, PC12 <– (SP+1)PC3-0 <– (SP+2)PC7-4 <– (

292µPD750008 USER'S MANUALRemark "Function" in this section is applicable to the µPD750008 whose program counter consists of13 bits (ad

293CHAPTER 11 INSTRUCTION SETPUSH BSFunction: (SP–1) <– MBS, (SP–2) <– RBS, SP <– SP–2Saves the contents of the memory bank select register

294µPD750008 USER'S MANUALDI IExxxFunction: IExxx <– 0 xxx = N5, N2-0Resets an interrupt enable flag (IExxx) to 0 to disable an interrupt.

295CHAPTER 11 INSTRUCTION SETCaution Before this instruction can be executed, MBE = 0 or (MBE = 1, MBS = 15) must be set.Only 4 or 6 can be specified

296µPD750008 USER'S MANUALGETI taddrFunction: taddr = T5-0, 0 : 20H-7FHFor the µPD750008[Mk I mode]• When a table defined by the TBR instructio

297CHAPTER 11 INSTRUCTION SETCaution All 2-byte instructions (except the BRCB instruction and CALLF instruction) set in thereference table must be 2

298µPD750008 USER'S MANUALExampleMOV HL, #00HMOV XA, #FFH are replaced with GETI instructions.CALL SUB1BR SUB2ORG 20HHL00: MOV HL, #00HXAFF:

299Masked ROM0000H - 1F7FH(8064 x 8 bits)75X standard CPU31.3 ms0.95, 1.91, 15.3 µs(when operating at4.19 MHz)NCP21Not provided000H - 0FFH2-byte stack

12µPD750008 USER'S MANUAL2.2 PIN FUNCTIONS2.2.1 P00-P03 (PORT0) : Input Pins Used Also for INT4, SCK, SO/SB0 and SI/SB1P10-P13 (PORT1) : In

300µPD750008 USER'S MANUALItem(2/2)SOS registerSerial interfaceFeedback resistor cutflag (SOS.0)Sub-oscillator current cutflag (SOS.1)Register ba

301APPENDIX B DEVELOPMENT TOOLSThe following development tools are provided for the development of a system which employs theµPD750008. In the 75XL

302µPD750008 USER'S MANUALPROM programming toolsNote These software products cannot use the task swap function, which is available in MS-DOS Ver.

303Debugging ToolsThe in-circuit emulators (IE-75000-R and IE-75001-R) are provided to debug programs used for theµPD750008.The following system is sh

304µPD750008 USER'S MANUALOS for IBM PCThe following IBM PC OSs are supported.OS VersionPC DOS Ver. 3.1 to Ver. 6.3J6.1/VNote to J6.3/VNoteMS-DOS

305APPENDIX B DEVELOPMENT TOOLSTarget sysytemNote 2Emulation probeEP-75008CU-REP-75008GB-RIn-circuit emulatorIE-75000-R orIE-75001-REmulation boar

306µPD750008 USER'S MANUALDrawings of the Conversion Socket (EV-9200G-44) and Recommended Pattern on BoardsFigure B-1. Drawings of the EV-9200G-

307APPENDIX B DEVELOPMENT TOOLSFigure B-2. Recommended Pattern on Boards for the EV-9200G-44 (Reference)EV-9200G-44-P0Caution Dimensions of mount pa

308µPD750008 USER'S MANUAL[MEMO]

309APPENDIX C MASKED ROM ORDERING PROCEDUREAfter program development is completed, the masked ROM is ordered by the following procedure:<1> Adv

13CHAPTER 2 PIN FUNCTIONS2.2.2 P20-P23 (PORT2) : I/O Pins Used Also for PTO0, PTO1, PCL, and BUZP30-P33 (PORT3) : I/O Pins Used Also for MD0-MD3Not

310µPD750008 USER'S MANUAL[MEMO]

311APPENDIX D INSTRUCTION INDEXD.1 INSTRUCTION INDEX (BY FUNCTION)[Transfer instructions]MOV A,#n4 ... 245, 264MOV reg1,#n4 ... 245, 265MOV XA,#n8

312µPD750008 USER'S MANUALOR A,@HL ... 247, 277OR XA,rp’ ... 247, 277OR rp’1,XA ... 247, 278XOR A,#n4 ... 247, 278XOR A,@HL ... 247, 278XOR XA,rp

313BRA !addr1 ... 251, 285BRCB !caddr ... 251, 286TBR addr ... 256, 288[Subroutine stack control instructions]CALLA !addr1 ... 251, 289CALL !addr ...

314µPD750008 USER'S MANUALD.2 INSTRUCTION INDEX (ALPHABETICAL ORDER)[A]ADDC A,@HL ... 246, 274ADDC rp’1,XA .. 246, 275ADDC XA,rp’ ... 246, 275A

315MOV A,@rpa1 ... 245, 265MOV HL,#n8 ... 245, 265MOV mem,A ... 245, 267MOV mem,XA ... 245, 267MOV reg1,A ... 245, 268MOV reg1,#n4 ... 245, 265MOV rp’

316µPD750008 USER'S MANUALSKT pmem.@L ... 248, 283SKT @H+mem.bit ... 248, 283SKTCLR fmem.bit ... 248, 283SKTCLR pmem.@L ... 248, 283SKTCLR @H+mem

317APPENDIX E HARDWARE INDEXE.1 HARDWARE INDEX (ALPHABETICAL ORDER WITH RESPECT TO THE HARDWARE NAME)[A]Acknowledge detection flag ... 132Acknowled

318µPD750008 USER'S MANUAL[W]Wake-up function specification bit ... 128Watchdog timer enable flag ... 101[R]Register bank enable flag ... 34, 64R

319E.2 HARDWARE INDEX (ALPHABETICAL ORDER WITH RESPECT TO THE HARDWARE SYMBOL)APPENDIX E HARDWARE INDEX[A]ACKD ... 132ACKE ... 132ACKT ... 132[B]BS

14µPD750008 USER'S MANUAL2.2.6 PCL: Output Pin Used Also for Port 2This is the programmable clock output pin. It is used to supply the clock

320µPD750008 USER'S MANUAL[S]SBIC ... 131SBS ... 46, 58SCC ... 88SIO ... 134SK0, SK1, SK2 ... 63SOS ... 93SP ... 58SVA ... 134[T]T0 ... 109T1 ...

321APPENDIX F REVISION HISTORYMajor revisions in this edition are shown below. The revised chapters refer to this edition.Edition Major revisions fr

322µPD750008 USER'S MANUAL[MEMO]

15CHAPTER 2 PIN FUNCTIONSINT0 has a noise eliminator. Two different sampling clocks for noise elimination can be switched. Theacceptable width of a

16µPD750008 USER'S MANUAL2.2.14 XT1, XT2These pins are used for connection to a crystal for subsystem clock oscillation.An external clock can a

17CHAPTER 2 PIN FUNCTIONS2.2.18 IC (for the µPD750004, µPD750006, and µPD750008 only)The internally connected (IC) pin is used to set the µPD750008

18µPD750008 USER'S MANUALType B-C2.3 PIN INPUT/OUTPUT CIRCUITSFigure 2-1 shows schematic diagrams of the I/O circuitry of the µPD750008.Figure

19CHAPTER 2 PIN FUNCTIONSP.U.R.: Pull-Up ResistorP.U.R.VDDP.U.R.enableP-chIN/OUTDataOutputdisableType DType AType E-BType M-CFigure 2-1. Pin Input

Major ChangesPage DescriptionAll The 44-pin plastic QFP package has been changed from µPD750008GB-xxx-3B4to µPD750008GB-xxx-3BS-MTX.The µPD75P0016 und

20µPD750008 USER'S MANUAL2.4 CONNECTION OF UNUSED PINSTable 2-3. Connection of Unused PinsPin name Recommended connectionP00/INT4 To be connec

21CHAPTER 3 FEATURES OF THE ARCHITECTURE AND MEMORY MAPCHAPTER 3 FEATURES OF THE ARCHITECTURE AND MEMORY MAPThe 75XL series architecture of the µPD7

22µPD750008 USER'S MANUALSET1 MBECLR1 MBESET1 MBEMBE = 1<Main program><Subroutine>MBE = 0MEB = 1CLR1 MBEMBE = 0RET <Interrup

23CHAPTER 3 FEATURES OF THE ARCHITECTURE AND MEMORY MAP3.1.2 Data Memory Addressing ModesWith the architecture of the µPD750008, seven addressing m

24µPD750008 USER'S MANUALFigure 3-2. Data Memory Organization and Addressing Range of Each Addressing ModeRemark – : Don't careAddressing

25CHAPTER 3 FEATURES OF THE ARCHITECTURE AND MEMORY MAPTable 3-1. Addressing ModesAddressing modeRepresentationSpecified addressformat1-bit direct m

26µPD750008 USER'S MANUAL(2) 4-bit direct addressing (mem)In this addressing mode, the operand of an instruction directly specifies any area in t

27CHAPTER 3 FEATURES OF THE ARCHITECTURE AND MEMORY MAPExample 2. Eight-bit data is latched into the serial interface shift register (SIO), and the t

28µPD750008 USER'S MANUALExample 2. The data memory of 00H to FFH is cleared to 0.CLR1 RBECLR1 MBEMOV XA,#00HMOV HL,#04HLOOP: MOV @HL,A ; (HL) &

29CHAPTER 3 FEATURES OF THE ARCHITECTURE AND MEMORY MAP(5) 8-bit register indirect addressing (@HL)In this addressing mode, the data pointer (HL regi

PREFACEReaders This manual is intended for engineers who want to learn the capabilities of theµPD750004, µPD750006, µPD750008, and µPD75P0016 to devel

30µPD750008 USER'S MANUAL(a) Specific address bit direct addressing (fmem.bit)In this addressing mode, peripheral equipment that frequently perfo

31CHAPTER 3 FEATURES OF THE ARCHITECTURE AND MEMORY MAP(b) Specific address bit register indirect addressing (pmem.@L)In this addressing mode, the bi

32µPD750008 USER'S MANUAL(c) Specific 1-bit direct addressing (@H+mem.bit)This addressing mode enables any bit in the data memory space to be man

33CHAPTER 3 FEATURES OF THE ARCHITECTURE AND MEMORY MAP(7) Stack addressingThis addressing mode is used for save/restoration operation in interrupt p

34µPD750008 USER'S MANUAL3.2 GENERAL REGISTER BANK CONFIGURATIONThe µPD750008 contains four register banks, each consisting of eight general re

35CHAPTER 3 FEATURES OF THE ARCHITECTURE AND MEMORY MAPFigure 3-4. Example of Register Bank SelectionThe setting of the RBS can be modified for subr

36µPD750008 USER'S MANUAL(2) When used as an 8-bit registerWhen the general register area is used on an 8-bit basis, the register pairs in the re

37CHAPTER 3 FEATURES OF THE ARCHITECTURE AND MEMORY MAPFigure 3-5. General Register Configuration (4-bit Processing)XHDBXHDBXHDBXHDB0

38µPD750008 USER'S MANUALFigure 3-6. General Register Configuration (8-bit Processing)XAHLDEBCXA’HL’DE’BC’00H02H04H06H08H0AH0CH0EH

39CHAPTER 3 FEATURES OF THE ARCHITECTURE AND MEMORY MAP3.3 MEMORY-MAPPED I/OThe µPD750008 employs memory-mapped I/O, which maps peripheral hardware

Notation Data bit significance : Higher-order bits on the left sideLower-order bits on the right sideActive low : xxx (Pin and signal names are oversc

40µPD750008 USER'S MANUALFigure 3-7. µPD750008 I/O Map (1/5)Notes 1. Can be manipulated separately as the RBS and MBS in 4-bit units.Can also be

41CHAPTER 3 FEATURES OF THE ARCHITECTURE AND MEMORY MAPFigure 3-7. µPD750008 I/O Map (2/5)Notes 1. TOE0: Timer/event counter output enable flag (W)

42µPD750008 USER'S MANUALFigure 3-7. µPD750008 I/O Map (3/5)Remarks 1. IExxx : Interrupt enable flag2. IRQxxx : Interrupt request flagNotes 1.

43CHAPTER 3 FEATURES OF THE ARCHITECTURE AND MEMORY MAPFigure 3-7. µPD750008 I/O Map (4/5)Note Whether a bit can be read or written depends on the

44µPD750008 USER'S MANUALFigure 3-7. µPD750008 I/O Map (5/5)Notes 1. Bit 1 can be read or written only in serial operation enable mode. It can

45CHAPTER 4 INTERNAL CPU FUNCTIONSCHAPTER 4 INTERNAL CPU FUNCTIONS4.1 Mk I MODE/Mk II MODE SWITCH FUNCTIONS4.1.1 Differences between Mk I Mode a

46µPD750008 USER'S MANUAL4.1.2 Setting of the Stack Bank Selection Register (SBS)The Mk I mode and Mk II mode are switched by stack bank select

47CHAPTER 4 INTERNAL CPU FUNCTIONSPC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0PC13PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0PC11PC11 PC10

48µPD750008 USER'S MANUAL4.3 PROGRAM MEMORY (ROM):4096 WORDS x 8 BITS (µPD750004: MASKED ROM)6144 WORDS x 8 BITS (µPD750006: MASKED ROM)8192

49CHAPTER 4 INTERNAL CPU FUNCTIONSFigure 4-3. Program Memory Map (in µPD750004)Note Can be used only in the MkII mode.Remark In addition to the abov

*Related documents Some documents are preliminary editions, but they are not so specified in the tablesbelow.Documents related to devicesDocument Name

50µPD750008 USER'S MANUALFigure 4-4. Program Memory Map (in µPD750006)Note Can be used only in the MkII mode.Remark In addition to the above, th

51CHAPTER 4 INTERNAL CPU FUNCTIONSFigure 4-5. Program Memory Map (in µPD750008)Note Can be used only in the MkII mode.Remark In addition to the abov

52µPD750008 USER'S MANUALFigure 4-6. Program Memory Map (in µPD75P0016)Note Can be used only in the MkII mode.Remark In addition to the above, t

53CHAPTER 4 INTERNAL CPU FUNCTIONS4.4 DATA MEMORY (RAM): 512 WORDS x 4 BITSThe data memory consists of a data area and peripheral hardware area as

54µPD750008 USER'S MANUAL4.4.2 Specification of a Data Memory BankIf the memory bank enable flag (MBE) enables bank specification (MBE = 1), a

55CHAPTER 4 INTERNAL CPU FUNCTIONSData memory is undefined when it is reset. For this reason, it is to be initialized to zero (RAM clear) usuallyat

56µPD750008 USER'S MANUAL4.5 GENERAL REGISTER: 8 x 4 BITS x 4 BANKSThe general registers are mapped to particular addresses in data memory. F

57CHAPTER 4 INTERNAL CPU FUNCTIONSFigure 4-9. Register Pair Format4.6 ACCUMULATORIn the µPD750008, the A register and XA register pair function as

58µPD750008 USER'S MANUAL4.7 STACK POINTER (SP) AND STACK BANK SELECT REGISTER (SBS)The µPD750008 uses static RAM as stack memory (LIFO scheme)

59CHAPTER 4 INTERNAL CPU FUNCTIONSFigure 4-11. Format of Stack Pointer and Stack Bank Select RegisterNote The Mk I mode and Mk II mode can be switch

[MEMO]

60µPD750008 USER'S MANUALPC11 - PC8MBESP + 2 PC3 - PC0PC7 - PC4SP + 4 IST1CYSP + 6SP + 1SP + 3SP + 5StackRBEPC12IST0SK2MBESK1RBESK0RETI instructi

61CHAPTER 4 INTERNAL CPU FUNCTIONSFigure 4-15. Data Restored from the Stack Memory (Mk II Mode)Notes 1. PC12 and PC13 are 0 in the µPD750004. PC13

62µPD750008 USER'S MANUAL4.8 PROGRAM STATUS WORD (PSW): 8 BITSThe program status word (PSW) consists of various flags closely associated with

63CHAPTER 4 INTERNAL CPU FUNCTIONSTable 4-4. Carry Flag Manipulation InstructionsInstruction (mnemonic) Carry flag operation/processingInstruction d

64µPD750008 USER'S MANUALTable 4-5. Information Indicated by the Interrupt Status FlagIST1 IST0 Status of processing Processing and interrupt co

65CHAPTER 4 INTERNAL CPU FUNCTIONSWhen the RBE is reset to 0, register bank 0 is always selected as general registers, regardless of the settingof th

66µPD750008 USER'S MANUALTable 4-6. Register Bank to Be Selected with the RBE and RBSBank 0 is always selected.RBERBS3210000xxBank 0 is selected

67CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONSCHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS5.1 DIGITAL I/O PORTSThe µPD750008 employs the memory mapped I/O m

68µPD750008 USER'S MANUAL5.1.1 Types, Features, and Configurations of Digital I/O PortsTable 5-1 lists the types of digital I/O ports.Figures 5-2

69CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONSFigure 5-2. Configurations of Ports 0 and 1Internal bus8 CSIMSelector SelectorP01 output latchInternal S

- i -CONTENTSCHAPTER 1 GENERAL ...

70µPD750008 USER'S MANUALFigure 5-3. Configurations of Ports 2 and 7Note For port 7 onlyMPXInput bufferPMm = 0Key interruptNoteOutputlatchPMm

71CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONSFigure 5-4. Configurations of Ports 3n and 6n (n = 0 to 3)Note For port 6n onlyBit m of POGAPull-up resis

72µPD750008 USER'S MANUALFigure 5-5. Configurations of Ports 4 and 5Internal busInput bufferMPXVDDPm0Pm1Pm2Pm3PMm = 0PMm = 1PMmOutput latchPull

73CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONSFigure 5-6. Configuration of Port 8Internal busP80P81Bit 0 ofPOGBPull-up resistorVDDP-chPM8OuputlatchMP

74µPD750008 USER'S MANUAL5.1.2 I/O Mode SettingThe I/O mode of each I/O port is set by the port mode register as shown in Figure 5-7. The I/O mo

75CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONSFigure 5-7. Formats of Port Mode Registers01Input mode (Output buffer off)Output mode (Output buffer on)Con

76µPD750008 USER'S MANUAL5.1.3 Digital I/O Port Manipulation InstructionsAll I/O ports contained in the µPD750008 are mapped to data memory spa

77CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS(3) 8-bit manipulation instructionsThe MOV, XCH, and SKE instructions as well as the IN and OUT instructions

78µPD750008 USER'S MANUALTable 5-2. I/O Pin Manipulation Instructions PORT PORT PORT PORT PORT PORT PORT PORT PORT PORTInstruction

79CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS5.1.4 Digital I/O Port OperationWhen a data memory manipulation instruction is executed for a digital I/O po