NEC 2400 ipx User Manual download pdf (Page 236)

CHAPTER 3 NDA-24296

Revision 1.0

Phase Lock Oscillator

The source clock of the clock subordinate office is either the digital clock supply (DCS) or the digital interface

clock (DIU0 - DIU3). When clock source failure has occurred, the PLO chooses another clock source

automatically in the order of:

6. PLO changeover or the PLO internal oscillator drifting

The PLO can output the clock signals (CLK) and the frame head signals (FH) as follows:

• 32.768 MHz CLK

• 5 msec × “n” FH

NEC 2400 ipx User Manual Page 236